FinFET Devices with Unique Fin Shape and the Fabrication Thereof

• US 20150263003A1
• Filed: 03/13/2014
• Published: 09/17/2015
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Wu, Cheng-Hsien, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Granted Patent: US 9,548,303 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

Claims

1. A semiconductor device, comprising:

a substrate;

a dielectric layer disposed over the substrate; and

a fin structure disposed over the dielectric layer;

wherein;

the fin structure contains a semiconductor material; and

the dielectric layer disposed below the fin structure includes a lateral recess.

2. The semiconductor device of claim 1, wherein the semiconductor device includes a p-channel metal-oxide-semiconductor (PMOS) FinFET and an n-channel metal-oxide-semiconductor (NMOS) FinFET, and wherein the fin structure is an NMOS fin structure of the NMOS FinFET.

3. The semiconductor device of claim 2, wherein the PMOS FinFET includes:

a silicon germanium layer disposed over the substrate;

a silicon layer disposed over the silicon germanium layer; and

a PMOS fin structure disposed over the silicon layer, wherein the PMOS fin structure contains silicon germanium.

4. The semiconductor device of claim 1, wherein the fin structure includes a [551] surface or a [661] surface.

5. The semiconductor device of claim 1, wherein the fin structure includes a narrower top portion and a wider bottom portion.

6. The semiconductor device of claim 1, wherein:

the fin structure contains silicon; and

the dielectric layer includes a silicon germanium oxide layer disposed over the substrate and a silicon oxide layer disposed over the silicon germanium layer.

7. The semiconductor device of claim 1, wherein an interface between the substrate and the dielectric layer is oxidized.

8. A semiconductor device, comprising:

a p-channel metal-oxide-semiconductor (PMOS) FinFET that includes;

a substrate;

a silicon germanium layer disposed over the substrate;

a silicon layer disposed over the silicon germanium layer; and

a PMOS fin disposed over the silicon layer, wherein the PMOS fin contains silicon germanium; and

an n-channel metal-oxide-semiconductor (NMOS) FinFET that includes;

the substrate;

a silicon germanium oxide layer disposed over the substrate;

a silicon oxide layer disposed over the silicon germanium oxide layer; and

an NMOS fin disposed over the silicon oxide layer, wherein the NMOS fin contains silicon, and wherein the silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction, the concave recess being partially disposed below the NMOS fin.

9. The semiconductor device of claim 8, wherein at least one of the PMOS fin and the NMOS fin includes a [551] surface or a [661] surface.

10. The semiconductor device of claim 8, wherein the PMOS fin and the NMOS fin each have bottom portions that are wider than top portions.

11. The semiconductor device of claim 8, wherein portions of the substrate below the silicon germanium oxide layer is oxidized.

12. A method of fabricating a semiconductor device having a p-channel metal-oxide-semiconductor (PMOS) region and an n-channel metal-oxide-semiconductor (NMOS) region, the method comprising:

forming a first semiconductor layer over the substrate, the first semiconductor layer spanning across both the PMOS region and the NMOS region;

forming a second semiconductor layer over the first semiconductor layer;

forming a plurality of recesses that each extend through the first semiconductor layer and the second semiconductor layer, the recesses being formed in both the PMOS region and the NMOS region;

forming a first protective layer to cover the recesses in the PMOS region but not the recesses in the PMOS region;

transforming a portion of the second semiconductor layer in the NMOS region into an insulating layer;

thereafter removing the first protective layer; and

thereafter forming shallow trench isolations (STIs) in the recesses in both the PMOS region and the NMOS region.

13. The method of claim 12, further comprising, after the forming of the STIs:

forming a second protective layer over the second semiconductor layer and over the STIs in the NMOS region but not in the PMOS region;

thereafter partially removing the second semiconductor layer in the PMOS region while leaving remaining portions of the second semiconductor layer to be disposed over the first semiconductor layer in the PMOS region;

forming a third layer over the remaining portions of the second semiconductor layer in the PMOS region;

partially removing the STIs in both the PMOS region and the NMOS region, thereby defining;

a plurality of PMOS fins that include at least a plurality of remaining segments of the third layer laterally exposed by the removal of the STIs in the PMOS region; and

a plurality of NMOS fins that include at least a plurality of remaining segments of the first semiconductor layer laterally exposed by the removal of the STIs in the NMOS region;

reshaping the PMOS fins and the NMOS fins; and

performing a cleaning process to the semiconductor device.

14. The method of claim 13, wherein the reshaping is performed such that the PMOS fins and NMOS fins include [551] or [661] surfaces.

15. The method of claim 13, wherein the cleaning process is performed such that the PMOS fins have different geometries than the NMOS fins.

16. The method of claim 15, wherein the cleaning process is performed such that bottom portions of the NMOS fins are laterally recessed.

17. The method of claim 13, wherein the forming of the third layer comprises epi-growing silicon germanium as the third layer over the remaining portions of the second semiconductor layer in the PMOS region.

18. The method of claim 12, wherein:

the forming of the first semiconductor layer comprises epi-growing a silicon germanium as the first semiconductor layer over the silicon substrate; and

the forming of the second semiconductor layer comprises epi-growing silicon as the second semiconductor layer over the silicon germanium.

19. The method of claim 18, wherein the transforming comprises performing an oxidation process to transform the silicon germanium into silicon germanium oxide.

20. The method of claim 19, wherein the oxidation process is performed such that a portion of the silicon is transformed into silicon oxide.