Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY

• US 20150263010A1
• Filed: 03/14/2014
• Published: 09/17/2015
• Est. Priority Date: 03/14/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Wu, Wei Cheng, Huang, Chin-Yi, Liu, Shih-Chang, Wu, Chang-Ming
• Granted Patent: US 9,583,591 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary.

Claims

1. A method of forming an integrated circuit comprising:

providing a substrate with a planar top surface;

recessing a section of the substrate to a depth below the planar top surface to form recessed and un-recessed surfaces that are disposed horizontally on the substrate;

forming a pair of memory cells over the recessed surface; and

forming a high-k metal gate (HKMG) circuitry over the un-recessed surface.

2. The method of claim 1, further comprising forming a transition region between the recessed and the un-recessed surfaces that extends into the substrate, having an asymmetrical geometry along an axis that is perpendicular to the planar top surface of the substrate.

3. The method of claim 1, wherein:

the memory cells comprise a pair of control gates;

the HKMG circuitry comprises a sacrificial gate; and

top surfaces of the pair of control gates and the sacrificial gate are co-planar.

4. The method of claim 3, wherein forming the HKMG circuitry comprises a chemical mechanical polishing (CMP) process that stops at the top surfaces of the sacrificial gate as well as the pair of control gates.

5. The method of claim 1, wherein the depth of the recessed surface, ranges from approximately 150 Angstroms to 800 Angstroms.

6. A method of forming an integrated circuit comprising:

providing a silicon (Si) substrate with a planar top surface;

recessing a section of the Si substrate to a depth below the planar top surface to form recessed and un-recessed surfaces on the Si substrate;

forming active regions separated by isolation zones within the Si substrate;

forming a memory control gate over the recessed surface;

forming a sacrificial gate (HKMG) over the un-recessed surface;

forming an inter-layer dielectric (ILD) layer over the Si substrate; and

performing a chemical mechanical polishing (CMP) operation on the ILD layer, wherein the CMP operation stops to define top surfaces of the memory control gate for a memory cell and a sacrificial gate for a HKMG transistor.

7. The method of claim 6, wherein a first isolation zone formed in the recessed surface and a second isolation zone formed in the un-recessed surface have symmetric geometries along an axis that is perpendicular to the planar top surface of the Si substrate and a third isolation zone formed in a transition region between the recessed and the un-recessed surfaces, has an asymmetric geometry along the axis.

8. The method of claim 6, wherein recessing a section of the Si substrate comprises:

photo defining the section of the Si substrate that needs to recessed, to form a defined Si substrate surface;

growing an oxide on the defined Si substrate surface through wet oxidation; and

performing a first etch to remove the oxide grown on the defined Si substrate surface.

9. The method of claim 8, wherein the first etch comprises a combination of dry etch and wet etch or a wet etch only.

10. The method of claim 6, wherein recessing a section of the Si substrate comprises:

photo defining the section of the Si substrate that needs to be recessed, to form a defined Si substrate surface; and

dry etching the defined Si substrate surface to form the recessed surface.

11. The method of claim 6, wherein forming active regions separated by isolation zones comprises:

depositing a silicon nitride (SiN) layer over the Si substrate surface;

forming a mask over the SiN layer, the mask covering some portions of the SiN layer while leaving other regions of the SiN layer exposed;

performing a dry etch to remove exposed portions of the SiN layer and corresponding Si layer underneath;

depositing an STI (shallow trench isolation) oxide over the Si substrate;

polishing and leveling a step height of the STI oxide; and

removing the SiN layer from the Si substrate.

12. The method of claim 6, wherein forming a memory cell comprises:

forming source and drain regions in the active regions;

forming a pair of control gate structures comprising a thicker control gate over a wider yet thinner floating gate;

forming an erase gate between two adjacent control gate structures;

forming select gates on opposing sides of two adjacent control gate structures; and

forming a dielectric layer between all the gates of the memory cells.

13. The method of claim 6, wherein forming a HKMG transistor comprises:

forming a high-k dielectric layer over the Si substrate;

forming a metal etch-stopping layer over the high-k dielectric layer;

forming a sacrificial polysilicon layer over the metal etch-stopping layer;

patterning the sacrificial polysilicon layer and the layers underneath to form a sacrificial gate structure;

forming an inter-layer dielectric (ILD) layer over and surrounding the sacrificial gate structure;

performing the chemical mechanical polishing (CMP) on the ILD layer that stops at the top surface of the sacrificial polysilicon layer;

removing the sacrificial polysilicon layer, thereby forming an opening in the gate structure; and

forming a metal gate electrode in the opening, thereby forming a high-k metal gate.

14. The method of claim 6, wherein the CMP operation does not damage top surfaces of the control gates of the memory cell.

15. An integrated circuit comprising:

a substrate including a periphery region having a first substrate surface and a memory cell region having a second substrate surface, wherein the second substrate surface is recessed within the substrate relative to the first substrate surface;

a high k metal gate (HKMG) transistor disposed on the first substrate surface and including a HKMG sacrificial gate; and

two neighboring flash memory cells formed on the second substrate surface and including a pair of flash memory cell control gates, wherein top surfaces of the HKMG sacrificial gate and flash memory cell control gates are co-planar.

16. The integrated circuit of claim 15, further comprising a transition region arranged between the first substrate surface and the second substrate surface and extending into the substrate along an axis that is perpendicular to the first and second substrate surfaces, wherein the transition region is asymmetric about the axis.

17. The integrated circuit of claim 15, wherein the two neighboring flash memory cells further comprises:

a pair of control gate structures comprising a flash memory control gate disposed above a floating gate;

a select gate disposed on opposing sides of each of the control gate structures; and

an erase gate disposed between the control gate structures.

18. The integrated circuit of claim 17, wherein the floating gates, control gates, erase gate and the sacrificial gate of the HKMG transistor comprise poly silicon.

19. The integrated circuit of claim 15, wherein the first and second substrate surfaces comprise source/drain regions disposed within.

20. The integrated circuit of claim 15, wherein the HKMG transistor comprises a static random access memory (SRAM) cell, an input/output cell or a core cell.