STACKED SEMICONDUCTOR DEVICE

• US 20150263088A1
• Filed: 03/17/2014
• Published: 09/17/2015
• Est. Priority Date: 03/17/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Reznicek, Alexander, Schepis, Dominic J.
• Granted Patent: US 9,224,811 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin.

Claims

1. A stacked semiconductor device fabrication process comprising:

forming a lattice-fin upon a semiconductor substrate;

forming a gate upon the semiconductor substrate surrounding a portion of the lattice-fin;

forming vertically stacked self-aligned nanowires by selectively removing a plurality of layers from the lattice-fin, and;

forming first epitaxy upon sidewalls of a plurality of vertically stacked self-aligned nanowires in a first nanowire group, the first epitaxy merging the first nanowire group in source and drain regions of the stacked semiconductor device.

2. The semiconductor device fabrication process of claim 1, further comprising:

forming a super-lattice upon the semiconductor substrate, the super-lattice comprising a first layered lattice formed upon the semiconductor substrate, an inter-lattice material formed upon the first layered lattice, and a second layered lattice formed upon the inter-lattice material.

3. The semiconductor device fabrication process of claim 2, wherein the first layered lattice comprises alternating first semiconductor layers and second semiconductor layers and wherein the second layered lattice comprises oppositely orientated alternating first semiconductor layers and second semiconductor layers.

4. The semiconductor device fabrication process of claim 3, wherein the lattice-fin is formed from the super-lattice and wherein the stacked self aligned nanowires are formed by removing the first semiconductor layers.

5. The semiconductor device fabrication process of claim 3, wherein the lattice-fin is formed from the super-lattice and wherein the stacked self aligned nanowires are formed by removing the second semiconductor layers.

7. The semiconductor device fabrication process of claim 1, further comprising:

forming second epitaxy upon sidewalls of a plurality of nanowires in a second nanowire group, the second epitaxy merging the plurality of nanowires in the second nanowire group in source and drain regions of the stacked semiconductor device.

8. The semiconductor device fabrication process of claim 7, wherein the merged first nanowire group forms a first field effect transistor (FET) structure of opposite polarity relative to a second FET structure formed from the merged second nanowire group.

9. The semiconductor device fabrication process of claim 1, wherein the gate is a dummy gate structure.

6. (canceled)

10-20. -20. (canceled)