COMMON SOURCE OXIDE FORMATION BY IN-SITU STEAM OXIDATION FOR EMBEDDED FLASH

• US 20150263123A1
• Filed: 03/13/2014
• Published: 09/17/2015
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Yu-Hung, Wu, Cheng-Ta, Tu, Yeur-Luen, Tsai, Chia-Shiung, Lee, Ru-Liang, Kao, Ming-Hsiang, Li, I-Ting
• Granted Patent: US 9,679,980 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

Claims

1. A memory cell, comprising:

a common source oxide layer located over a source region disposed along a top surface of a semiconductor substrate;

a first drain region disposed along the top surface of the semiconductor substrate at a position that is laterally separated from the source region by a first channel region; and

a common erase gate disposed onto the common source oxide layer, wherein the common erase gate comprises a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

2. The memory cell of claim 1, wherein the source region comprises a dopant concentration that is greater than or equal to 1E 19 cm⁻

3.

3. The memory cell of claim 1, wherein the common source oxide layer has a density greater than a density of an oxide formed using a wet furnace oxidation process.

4. The memory cell of claim 1, further comprising:

a second drain region disposed along the top surface of the semiconductor substrate on an opposite side of the source region as the first drain region at a position that is laterally separated from the source region by a second channel region;

a first floating gate separated from the first channel region by a first floating gate oxide layer abutting the common source oxide layer; and

a second floating gate separated from the second channel region by a second floating gate oxide layer abutting the common source oxide layer.

5. The memory cell of claim 4, further comprising:

a first control gate disposed over the first floating gate; and

a second control gate disposed over the second floating gate.

6. The memory cell of claim 5, wherein the first control gate is separated from the common erase gate by a first spacer structure abutting the first control gate and additional dielectric material, wherein a thickness of the first spacer structure is approximately equal to a thickness of the additional dielectric material between the first control gate and the common erase gate.

7. The memory cell of claim 1, wherein the common source oxide layer comprises a curved bottom surface that opposes the substantially flat top surface, and which abuts the source region.

8. The memory cell of claim 1, further comprising:

a first select gate disposed along a side of the first floating gate opposing the common erase gate, wherein the first select gate is coupled to a first word line; and

a second select gate disposed along a side of the second floating gate opposing the common erase gate, wherein the second select gate is coupled to a second word line.

9. An embedded flash memory cell, comprising:

a semiconductor substrate comprising a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region;

a common source oxide layer having a bottom surface abutting the common source region and a top surface;

a first floating gate separated from the first channel region by a first floating gate oxide layer overlying the semiconductor substrate at a first position abutting the common source oxide layer;

a second floating gate separated from the second channel region by a second floating gate oxide layer overlying the semiconductor substrate at a second position abutting the common source oxide layer; and

a common erase gate disposed onto the common source oxide layer and having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

10. The flash memory cell of claim 9, wherein the common source oxide layer comprises a curved bottom surface that opposes the substantially flat top surface, and which abuts the common source region.

11. The flash memory cell of claim 9, wherein the common source oxide layer has a height below the common erase gate having a range of between approximately 10 nm and approximately 40 nm.

12. A method of forming a memory cell, comprising:

forming a source region and a drain region within a semiconductor substrate;

performing an in-situ steam generation (ISSG) process to form a common source oxide layer over the source region; and

forming a gate structure onto the common source oxide layer, wherein the gate structure has a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

13. The method of claim 12, further comprising:

forming a first floating gate over a first floating gate oxide layer disposed on the semiconductor substrate at a first position between the source region and a first drain region;

forming a second floating gate over a second floating gate oxide layer disposed on the semiconductor substrate at a second position between the source region and a second drain region, wherein the second drain region is located on an opposite side of the source region than the first drain region; and

forming a common erase gate onto the common source oxide layer, wherein the common erase gate has the substantially flat bottom surface abutting the substantially flat top surface of the common source oxide layer.

14. The method of claim 13, further comprising:

forming a first control gate over the first floating gate, and a second control gate over the second floating gate; and

forming a first select gate coupled to a first word line along a side of the floating gate opposing the common erase gate and a second select gate coupled to a second word line along a side of the floating gate opposing the common erase gate.

15. The method of claim 14, further comprising:

forming a first spacer structure abutting the first control gate and separated from the common erase gate by an additional dielectric material, wherein a thickness of the first spacer structure is approximately equal to a thickness of the additional dielectric material between the first control gate and the common erase gate.

16. The method of claim 12, wherein the common source oxide layer comprises a curved bottom surface opposing the top surface.

17. The method of claim 12, wherein performing the ISSG process comprises:

providing the semiconductor substrate into a processing chamber held at a first pressure;

operating a heating element to increase a temperature of the semiconductor substrate; and

introducing a gas mixture comprising hydrogen and oxygen into the processing chamber,

wherein upon coming into contact with the heated semiconductor substrate, the gas mixture forms hydroxide (OH) and atomic oxygen, which react with the semiconductor substrate to form a silicon oxide.

18. The method of claim 17, wherein the first pressure is in a range of between approximately 1 torr and approximately 20 torr.

19. The method of claim 17, wherein the temperature of the semiconductor substrate is in a range of between approximately 900°

C. and 1100°

C.

20. The method of claim 17, wherein the gas mixture comprises between approximately 1% and approximately 50% hydrogen (H₂) and between approximately 99% and approximately 50% oxygen (O₂).