METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING STRESSOR

• US 20150263138A1
• Filed: 01/07/2015
• Published: 09/17/2015
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, JUN-SUK
• Granted Patent: US 9,299,812 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

Provided are methods of forming a semiconductor device having an embedded stressor. The method includes forming a fin active area on a substrate. A gate structure configured to cross the fin active area and cover a side surface of the fin active area, and a gate spacer on a sidewall of the gate structure are formed. Preliminary trenches are formed in the fin active area adjacent to both sides of the gate structure using an anisotropic etching process. An etching select area is formed by oxidizing the fin active area exposed to the preliminary trenches. Trenches are formed by removing the etching select area. A stressor is formed in each of the trenches.

Claims

1. A method of forming a semiconductor device, comprising:

forming a fin active area on a substrate;

forming a gate structure configured to cross the fin active area and cover a side surface of the fin active area, and a gate spacer on a sidewall of the gate structure;

forming trenches in the fin active area adjacent to both sides of the gate structure; and

forming stressors in the trenches,

wherein the forming of the trenches includes forming preliminary trenches by anisotropically etching the fin active area, forming an etching select area by oxidizing the fin active area exposed to the preliminary trenches, and removing the etching select area.

2. The method according to claim 1, wherein the forming of the etching select area includes a radical oxidation process.

3. The method according to claim 1, wherein the forming of the trenches includes forming the preliminary trenches by anisotropically etching the fin active area, and then performing a process of forming the etching select area in the fin active area and a process of removing the etching select area two or more times.

4. The method according to claim 1, wherein each of the trenches has a U-shape.

5. The method according to claim 1, further comprising:

forming halo areas configured to cover the stressors in the fin active area.

6. The method according to claim 1, wherein sidewalls of the trenches are arranged under the gate spacer, and have a substantially vertical profile.

7. The method according to claim 1, wherein, when one of sidewalls of the trenches is selected, and first to fourth quadrant points are defined on the selected sidewall thereof, the fourth quadrant point is located on an upper corner of the fin active area, the second quadrant point is located on a horizontal line passing through a vertical bisection point between a bottom and an upper end of the trench, and a straight line passing through the second quadrant point and the third quadrant point is substantially perpendicular to a surface of the substrate.

8. The method according to claim 7, wherein the fourth quadrant point is located on the straight line passing through the second quadrant point and the third quadrant point.

9. The method according to claim 7, wherein the fourth quadrant point is spaced apart from the straight line passing through the second quadrant point and the third quadrant point, and the fourth quadrant point is nearer a center of the gate structure than the second quadrant point and the third quadrant point.

10. The method according to claim 1, wherein the forming of the stressors comprises:

forming a first semiconductor layer in the trenches;

forming a second semiconductor layer on the first semiconductor layer, and

forming a third semiconductor layer on the second semiconductor layer,

wherein the first semiconductor layer and the second semiconductor layer include a different material from the fin active area.

11. The method according to claim 10, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed by a selective epitaxial growth (SEG) method.

12. The method according to claim 11, wherein each of the first semiconductor layer and the second semiconductor layer include a SiGe, and a Ge content in the second semiconductor layer is greater than that in the first semiconductor layer, and wherein the third semiconductor layer includes a Si.

13. The method according to claim 12, wherein the forming of the etching select area includes a thermal oxidation process.

14. A method of forming a semiconductor device, comprising:

forming an active area on a substrate;

forming a gate structure configured to cross the active area;

forming trenches in the active area adjacent to both sides of the gate structure; and

forming stressors in the trenches,

wherein the forming of the trenches includes forming preliminary trenches by anisotropically etching the active area, forming an etching select area in the preliminary trenches by oxidizing the active area using a radical oxidation process, and removing the etching select area.

15. The method according to claim 14, wherein sidewalls of the trenches have a profile substantially perpendicular to a surface of the substrate.

16. The method according to claim 14, wherein the forming of the trenches includes forming the preliminary trenches by anisotropically etching the active area, and then performing a process of forming the etching select area in the active area by the radical oxidation process and a process of removing the etching select area two or more times.

17. The method according to claim 14, wherein each of the trenches has a U-shape.

18. A method of forming a semiconductor device, comprising:

forming an fin active area on a substrate;

forming a gate structure configured to cross the fin active area;

forming preliminary trenches in the fin active area adjacent to both sides of the gate structure;

forming trenches by performing a process one or more times, the process including forming an etching select area in the preliminary trenches by oxidizing the fin active area using a radical oxidation process and removing the etching select area; and

forming a stressor by selective epitaxial growth method in each of the trenches.

19. The method according to claim 18, wherein sidewalls of the trenches have a profile substantially perpendicular to a surface of the substrate.

20. The method according to claim 18, wherein sidewalls of the stressor have a profile substantially perpendicular to a surface of the substrate.