FINFET Structure and Method for Fabricating the Same

• US 20150263159A1
• Filed: 03/17/2014
• Published: 09/17/2015
• Est. Priority Date: 03/17/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Chen, Guan-Lin, Liu, Chi-Wen, Wang, Chao Hsiung
• Granted Patent: US 9,520,498 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device comprises a substrate comprising silicon, a fin structure comprising a lower portion formed of silicon and enclosed by an isolation region, a middle portion formed of silicon-germanium-carbon, wherein the middle portion is enclosed by an oxide layer, an upper portion formed of silicon, wherein the upper portion comprises a channel and a silicon-carbon layer formed between the middle portion and the upper portion, a first source/drain region comprising a first silicon-phosphorus region and a first silicon-carbon layer formed underlying the first silicon-phosphorus region and a second source/drain region comprising a second silicon-phosphorus region and a second silicon-carbon layer formed underlying the second silicon-phosphorus region.

Claims

1. An apparatus comprising:

a substrate formed of a first semiconductor material;

a fin structure protruding over the substrate, wherein the fin structure comprises;

a lower portion formed of the first semiconductor material;

a middle portion formed of a second semiconductor material;

an upper portion formed of the first semiconductor material, wherein the upper portion comprises a channel connected between a first source/drain region and a second source/drain region; and

a first carbon doped layer formed between the middle portion and the upper portion;

a second carbon doped layer formed underlying the first source/drain region; and

a third carbon doped layer formed underlying the second source/drain region.

2. The apparatus of claim 1, further comprising:

a gate region wrapping the channel of the fin structure.

3. The apparatus of claim 1, wherein:

the first semiconductor material is silicon; and

the second semiconductor material is silicon-germanium-carbon (SiGeC).

4. The apparatus of claim 1, wherein:

the first carbon doped layer is formed of silicon-carbon (SiC);

the second carbon doped layer is formed of SiC; and

the third carbon doped layer is formed of SiC.

5. The apparatus of claim 1, wherein:

the second carbon doped layer is formed of silicon-carbon-phosphorus (SiCP); and

the third carbon doped layer is formed of SiCP.

6. The apparatus of claim 1, wherein:

the first source/drain region is formed of silicon-phosphorus (SiP); and

the second source/drain region is formed of SiP.

7. The apparatus of claim 1, wherein:

the middle portion of the fin structure comprises an oxide outer layer, and wherein the oxide outer layer is formed of SiGeOx, and wherein x is oxygen composition in atomic percentage.

8. A device comprising:

a substrate comprising silicon;

a fin structure protruding over the substrate, wherein the fin structure comprises;

a lower portion formed of silicon and enclosed by an isolation region;

a middle portion formed of silicon-germanium-carbon, wherein the middle portion is enclosed by an oxide layer;

an upper portion formed of silicon, wherein the upper portion comprises a channel; and

a silicon-carbon layer formed between the middle portion and the upper portion;

a first source/drain region comprising a first silicon-phosphorus region and a first silicon-carbon layer formed underlying the first silicon-phosphorus region; and

a second source/drain region comprising a second silicon-phosphorus region and a second silicon-carbon layer formed underlying the second silicon-phosphorus region.

9. The device of claim 8, wherein:

the first source/drain region is of a thickness in a range from about 30 nm to about 50 nm; and

the second source/drain region is of a thickness in a range from about 30 nm to about 50 nm.

10. The device of claim 8, wherein:

the oxide layer comprises SiGeOx, and wherein x is oxygen composition in atomic percentage.

11. The device of claim 8, wherein:

the silicon-carbon layer is of a thickness in a range from about 5 nm to about 15 nm.

12. The device of claim 11, wherein:

a carbon concentration of the silicon-carbon layer is from about 0.5% to about 2% in atomic percentage.

13. The device of claim 8, wherein:

a germanium concentration of the middle portion is from about 20% to about 45%; and

a carbon concentration of the middle portion is from about 0.5% to about 2%.

14. The device of claim 8, wherein:

the silicon-carbon layer further comprises phosphorus.

15. The device of claim 14, wherein:

a phosphorus concentration is in a range from about 1E20/cm3 to about 5E20/cm3.

16. A method comprising:

providing a substrate formed of a first semiconductor material;

recessing the substrate to form a fin enclosed by an isolation region;

recessing the fin to form a trench over a lower portion of the fin;

growing a second semiconductor material in the trench to form a middle portion of the fin through a first epitaxial process;

forming a first carbon doped layer over the lower portion through a second epitaxial process;

growing the first semiconductor material over the carbon doped layer to form an upper portion of the fin through a third epitaxial process;

forming a first source/drain region through a fourth epitaxial process, wherein a second carbon doped layer is formed underlying the first source/drain region; and

applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.

17. The method of claim 16, further comprising:

in-situ doping carbon during the first epitaxial process, wherein the second semiconductor material is silicon-germanium.

18. The method of claim 16, wherein:

the first semiconductor material is silicon.

19. The method of claim 16, wherein:

the first carbon doped layer comprises silicon-carbon.

20. The method of claim 16, wherein:

the second carbon doped layer comprises silicon-carbon.