JFET AND METHOD OF MANUFACTURING THEREOF
First Claim
1. A vertical JFET, comprising:
- a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface;
a source metallization arranged on the first surface;
a drain metallization arranged on the second surface; and
a gate metallization arranged on the first surface, wherein, in a sectional plane substantially perpendicular to the first surface, the semiconductor body comprises;
an n-doped first semiconductor region in ohmic contact with the drain metallization and the source metallization;
a plurality of p-doped second semiconductor regions in ohmic contact with the gate metallization, substantially extending to the first surface, spaced apart from one another and forming respective first pn-junctions with the first semiconductor region; and
a plurality of p-doped body regions in ohmic contact with the source metallization, spaced apart from one another, from the p-doped second semiconductor regions, from the first surface and from the second surface, and forming respective second pn-junctions with the first semiconductor region.
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Accused Products
Abstract
A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.
13 Citations
25 Claims
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1. A vertical JFET, comprising:
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a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface; a source metallization arranged on the first surface; a drain metallization arranged on the second surface; and a gate metallization arranged on the first surface, wherein, in a sectional plane substantially perpendicular to the first surface, the semiconductor body comprises; an n-doped first semiconductor region in ohmic contact with the drain metallization and the source metallization; a plurality of p-doped second semiconductor regions in ohmic contact with the gate metallization, substantially extending to the first surface, spaced apart from one another and forming respective first pn-junctions with the first semiconductor region; and a plurality of p-doped body regions in ohmic contact with the source metallization, spaced apart from one another, from the p-doped second semiconductor regions, from the first surface and from the second surface, and forming respective second pn-junctions with the first semiconductor region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A JFET, comprising:
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a semiconductor body comprising a semiconductor material that has a band-gap higher than about two electron volts and extends between a first surface and a second surface which runs substantially parallel to the first surface; a source metallization arranged on the first surface; a gate metallization arranged on the first surface; and a drain metallization arranged on the second surface, wherein, in a sectional plane substantially perpendicular to the first surface, the semiconductor body comprises; a first semiconductor region in ohmic contact with the source metallization and the drain metallization; at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region; and at least one body region forming a second pn-junction with the first semiconductor region, wherein the at least one body region is in ohmic contact with the source metallization, and wherein at least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions. - View Dependent Claims (13, 14, 15, 16)
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17. A method for producing a JFET, the method comprising:
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providing a semiconductor substrate having a first surface and comprising an n-doped first semiconductor layer; forming a hard mask on the first surface, the hard mask comprising openings defining first zones in the n-doped first semiconductor layer; implanting acceptor ions of a first maximum energy through the hard mask into the first zones; replacing the hard mask by an inverted mask comprising openings that are substantially complementary to the openings of the hard mask; implanting acceptor ions of a second maximum energy different to the first maximum energy through the inverted mask into second zones of the n-doped first semiconductor layer; carrying out at least one temperature step to activate the acceptor ions in the first zones and the second zones; forming on the first surface a gate metallization in ohmic contact with the second zones; and forming on the first surface a source metallization in ohmic contact with the first zones. - View Dependent Claims (18, 19, 20)
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21. A method for producing a JFET, the method comprising:
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providing a semiconductor substrate having a first side and comprising an n-doped first semiconductor layer extending to the first side; forming a mask on the first side so that the mask comprises in a sectional plane mask portions and openings arranged between adjacent mask portions; implanting acceptor ions through the mask into the first semiconductor layer, the acceptor ions having a first maximum energy so that at least a portion of the acceptor ions impacting on the mask portions penetrate through the mask portions and are implanted into the first semiconductor layer; removing the mask; and implanting donor ions from the first side into the first semiconductor layer. - View Dependent Claims (22, 23, 24, 25)
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Specification