FRONT-SIDE EMITTING MID-INFRARED LIGHT EMITTING DIODE FABRICATION METHODS
First Claim
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1. A method for manufacturing a mid-infrared LED, the method comprising:
- forming an electrical contact between a substrate and a first light emission stage using variable-period superlattices;
forming first and subsequent light emission stages to have double-heterostructure confinement configurations, with variable period semiconductor superlattices forming one or more charge injectors and minority carrier barriers;
forming cascaded light emission stages by forming semi-metallic tunneling junctions between light emission stages using a junction between layers of GaSb and InAs, or closely related alloys, doped with Si on both sides of the junction;
growing strain-balanced superlattices and heterostructures;
forming an electrical contact between a topmost light emission stage and an InAs current-spreading and ohmic contact layer using variable-period superlattices; and
growing a layer of GaSb or closely related alloy for etching light-extraction surface features.
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Abstract
Methods for fabricating mid-infrared light emitting diodes (LEDs) based upon antimonide-arsenide semiconductor heterostructures and configured into front-side emitting high-brightness LED die and other LED die formats.
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Citations
20 Claims
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1. A method for manufacturing a mid-infrared LED, the method comprising:
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forming an electrical contact between a substrate and a first light emission stage using variable-period superlattices; forming first and subsequent light emission stages to have double-heterostructure confinement configurations, with variable period semiconductor superlattices forming one or more charge injectors and minority carrier barriers; forming cascaded light emission stages by forming semi-metallic tunneling junctions between light emission stages using a junction between layers of GaSb and InAs, or closely related alloys, doped with Si on both sides of the junction; growing strain-balanced superlattices and heterostructures; forming an electrical contact between a topmost light emission stage and an InAs current-spreading and ohmic contact layer using variable-period superlattices; and growing a layer of GaSb or closely related alloy for etching light-extraction surface features. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method to an manufacture mid-infrared LED, the method comprising:
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defining geometry of weakly-coupled surface buttes using photolithography, with a butte size and a butte spacing adjusted to accommodate efficient light extraction at one or more wavelengths of the light emission layers; etching through most of a topmost epitaxial layer of GaSb, or closely related alloy, using a dry plasma-based etch with a Cl-based etch gas mixture; and completing an etch through a last portion of the topmost epitaxial layer of GaSb, or closely related alloy, using a chemically-selective wet etch based upon an ammonium hydroxide solution chosen to selectively stop etching on an underlaying InAs electrical contact layer. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method for fabricating a device emitting mid-infrared light, the method comprising:
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growing epitaxial crystalline semiconductor device layers by molecular beam epitaxy on a front surface of a semiconductor substrate of GaSb or closely related material, wherein the layers are comprised of InAs, GaAs, AlSb, and related alloys; forming strain-balanced heterostructures during molecular beam epitaxial growth that comprise light emitting structures cascaded by tunnel junctions; lithographically etching dielectric light output coupling surface structures into a topmost GaSb epitaxial layer; lithographically etching mesas and trenches through the heterostructure layers to define and isolate an active regions of the device; depositing and lithographically patterning a current-spreading front-surface metal electrical contact structure; depositing and lithographically patterning a front-side anti-reflection coating on one or more light extraction surface features; etching surfaces of the heterostructure sidewalls and depositing a chemical and electrical passivation coating; thinning the substrate, to decrease light absorption and increase thermal conduction, and polishing a backside of the substrate for forming a backside internal minor; depositing backside metals that form an internal minor, an electrical contact, and a surface layer for eutectic die attachment; and attaching a finished die to a light emitting diode package with eutectic solder or conducting epoxy and wire bonding to at least one frontside device bond pad.
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Specification