DELAY LOCKED LOOP

• US 20150263740A1
• Filed: 12/18/2014
• Published: 09/17/2015
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: Industry Academic Cooperation Foundation, SK Hynix Inc.
• Original Assignee: Industry Academic Cooperation Foundation, SK Hynix Inc.
• Inventors: JUNG, Dong-Hoon, KIM, Jin-Hyuk, RYU, Kyung-Ho, JUNG, Seong-Ook, OH, Byoung-Chan
• Granted Patent: US 9,154,140 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/10 for assuring initial synchronisation or for broadening the capture range

Abstract

A delay locked loop includes a variable delay line circuit configured to delay a pulse selection circuit output to generate an output signal, a delay model circuit to delay the output signal to generate a first feedback signal, a first phase comparator circuit to control the variable delay line circuit according to the input signal and the first feedback signal, a pulse generation circuit to generate a pulse signal according to the input signal and the first feedback signal, a pulse retainer circuit to delay the output signal to generate a second feedback signal, a pulse selection circuit to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation, and a second phase comparator circuit to control the variable delay line circuit according to the pulse selection circuit output and the output signal.

Claims

1. A delay locked loop for locking a delay between an input signal and an output signal, comprising:

a variable delay line circuit configured to delay a pulse selection circuit output to generate the output signal;

a delay model circuit configured to delay the output signal to generate a first feedback signal;

a first phase comparator circuit configured to control a delay amount of the variable delay line circuit depending on a phase difference between the input signal and the first feedback signal;

a pulse generation circuit configured to generate a pulse signal in response to the input signal and the first feedback signal during a tracking operation;

a pulse retainer circuit configured to delay the output signal to generate a second feedback signal during the tracking operation;

a pulse selection circuit configured to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation; and

a second phase comparator circuit configured to generate a delay control signal to control the delay amount of the variable delay line circuit depending on a phase difference between the pulse selection circuit output and the output signal during the tracking operation.

2. The delay locked loop of claim 1,

wherein a pulse width of the pulse signal is a sum of (i) the phase difference between the first feedback signal and the input signal and (ii) an initial delay amount of the variable delay line circuit.

3. The delay locked loop of claim 2,

wherein the pulse generation circuit forms a rising edge of the pulse signal according to a rising edge of the first feedback signal and forms a falling edge of the pulse signal according to a point of time which is determined by delaying a rising edge of the input signal by the initial delay amount of the variable delay line circuit.

4. The delay locked loop of claim 3,

wherein, after completion of the tracking operation, the pulse generation circuit generates the pulse signal having substantially the same waveform as the input signal.

5. The delay locked loop of claim 4,

wherein, after completion of the tracking operation, the pulse selection circuit selects an output of the pulse generation circuit as the pulse selection circuit output.

6. The delay locked loop of claim 1,

wherein the pulse selection circuit selects an output of the pulse generation circuit shortly after the pulse signal is generated by the pulse generation circuit, and

wherein the pulse selection circuit selects the second feedback signal when the pulse signal is subject to feedback of the first feedback signal.

7. The delay locked loop of claim 1,

wherein the second phase comparator completes the tracking operation when a falling edge of the pulse selection circuit output is aligned to a rising edge of the output signal.

8. The delay locked loop of claim 1,

wherein the variable delay line circuit comprises a first variable delay line circuit and a second variable delay line circuit,

wherein the second phase comparator circuit controls delay amounts of the first variable delay line circuit and the second delay line circuit during the tracking operation, and

wherein the first phase comparator circuit controls a delay amount of the second variable delay line circuit after the tracking operation completes.

9. The delay locked loop of claim 1,

wherein a delay amount of the pulse retainer circuit is the same as or more than a sum of (i) a time period necessary for the second phase comparator circuit to update the delay control signal and (ii) a time period necessary to update the delay amount of the variable delay line circuit in response to the updated delay control signal.

10. The delay locked loop of claim 9,

wherein the delay amount of the pulse retainer circuit is less than a delay amount of the delay model circuit.

11. The delay locked loop of claim 1, further comprising:

a duty ratio control circuit configured to control a duty ratio of a signal generated by the variable delay line circuit to provide the duty ratio controlled signal as the output signal.

12. The delay locked loop of claim 11,

wherein the duty ratio control circuit comprises:

an edge combiner circuit configured to combine the second feedback signal output from the pulse retainer circuit and the signal generated by the variable delay line circuit to generate the output signal; and

a third phase comparator circuit configured to control a delay amount of the pulse retainer circuit depending on a phase difference between the output signal and the second feedback signal.

13. The delay locked loop of claim 12,

wherein the edge combiner circuit generates the output signal having a rising edge according to a rising edge of the signal generated by the variable delay line circuit and having a falling edge according to a rising edge of the second feedback signal.