PRECISION HALF CELL FOR SUB-FEMTO UNIT CAP AND CAPACITIVE DAC ARCHITECTURE IN SAR ADC

• US 20150263754A1
• Filed: 03/10/2015
• Published: 09/17/2015
• Est. Priority Date: 03/16/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Keramat, Mansour, Chao, Yuan-Ju, Srinivas, Vijay
• Granted Patent: US 9,418,788 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01G 4/01 Form of self-supporting electrodes
• CPC Class Codes: H01G 4/129 containing a glassy phase, e.g. glass ceramic
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/38 Multiple capacitors, i.e. structural combinations of fixed capacitors
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

A capacitive device is disclosed, including a first conductor formed on a lower metal layer and coupled to a first terminal. A second conductor is formed on an upper metal layer and a plurality of wires is partitioned into groups, each group including one wire from a respective metal layer. First and second wires of each group are coupled to a second terminal. A third wire of each group, adjacent to the first wire, is coupled to the first conductor. A fourth wire of each group, adjacent to the second wire, is coupled to the second conductor. Fifth wires of a first subset of the groups are coupled to the second conductor and fifth wires of a second subset of the groups are coupled to the first conductor. The fifth wire of each group is adjacent to the first wire and the second wire.

Claims

1. A capacitive device, comprising:

a first conductor formed on a lower metal wiring layer of a plurality of metal wiring layers, wherein the first conductor is coupled to a first terminal;

a second conductor formed on an upper metal wiring layer of the plurality of metal wiring layers; and

a plurality of parallel wires partitioned into a plurality of groups, wherein parallel wires included in each group of the plurality of groups are formed on a respective one of a subset of the plurality of metal wiring layers, wherein the subset of the plurality of metal wiring layers is between the upper metal wiring layer and the lower metal wiring layer,

wherein;

a first parallel wire and a second parallel wire of each group of the plurality of groups is coupled to a second terminal;

a third parallel wire of each group of the plurality of groups is coupled to the first conductor, wherein the third parallel wire is adjacent to the first parallel wire;

a fourth parallel wire of each group of the plurality of groups is coupled to the second conductor, wherein the fourth parallel wire is adjacent to the second parallel wire;

a fifth parallel wire of each group of a first subset of the plurality groups is coupled to the second conductor, and wherein the fifth parallel wire of each group of a second subset of the plurality of groups is coupled to the first conductor; and

the fifth parallel wire of each group of the plurality of groups is adjacent to the first parallel wire and the second parallel wire.

2. The capacitive device of claim 1, wherein the first subset of the plurality of groups is mutually exclusive to the second subset of the plurality of groups.

3. The capacitive device of claim 2, wherein a number of groups included in the first subset of the plurality of groups is equal to a number of groups included in the second subset of the plurality of groups.

4. The capacitive device of claim 1, wherein an edge of the third parallel wire included in a given group of the plurality of groups is parallel to an edge of the third parallel wire included in any other given group of the plurality of groups.

5. The capacitive device of claim 1, wherein a dielectric material is included between each adjacent parallel wire in a given group of the plurality of groups.

6. The capacitive device of claim 1, wherein the second conductor is coupled to a third terminal.

7. The capacitive device of claim 6, wherein the third terminal is coupled to a ground voltage reference.

8. A method comprising:

receiving an input signal;

coupling the input signal to a first terminal of a capacitive device, wherein the capacitive device includes;

a first conductor formed on a lower metal wiring layer of a plurality of metal wiring layers, wherein the first conductor is coupled to the first terminal;

a second conductor formed on an upper metal wiring layer of the plurality of metal wiring layers; and

a plurality of parallel wires partitioned into a plurality of groups, wherein parallel wires included in each group of the plurality of groups are formed on a respective one of a subset of the plurality of metal wiring layers, wherein the subset of the plurality of metal wiring layers is between the upper metal wiring layer and the lower metal wiring layer,

wherein;

a first parallel wire and a second parallel wire of each group of the plurality of groups is coupled to a second terminal;

a third parallel wire of each group of the plurality of groups is coupled to the first conductor, wherein the third parallel wire is adjacent to the first parallel wire;

a fourth parallel wire of each group of the plurality of groups is coupled to the second conductor, wherein the fourth parallel wire is adjacent to the second parallel wire;

a fifth parallel wire of each group of a first subset of the plurality groups is coupled to the second conductor, and wherein the fifth parallel wire of each group of a second subset of the plurality of groups is coupled to the first conductor; and

the fifth parallel wire of each group of the plurality of groups is adjacent to the first parallel wire and the second parallel wire; and

coupling an output signal at the second terminal, wherein the output signal is dependent upon a voltage level across the capacitive device.

9. The method of claim 8, further comprising coupling the first terminal to a reference voltage dependent upon a determination that the voltage level across the capacitive device is the same as a voltage level of the input signal.

10. The method of claim 9, further comprising determining a value corresponding to the voltage level of the input signal.

11. The method of claim 8, wherein the first subset of the plurality of groups is mutually exclusive to the second subset of the plurality of groups and wherein a number of groups included in the first subset of the plurality of groups is equal to a number of groups included in the second subset of the plurality of groups.

12. The method of claim 8, wherein an edge of the third parallel wire included in a given group of the plurality of groups is aligned to an edge of the third parallel wire included in any other given group of the plurality of groups.

13. The method of claim 8, wherein the second conductor is coupled to a third terminal, and wherein the third terminal is coupled to a ground signal.

14. A system comprising:

a plurality of capacitors, wherein at least one capacitor of the plurality of capacitors includes;

a first conductor formed on a bottom metal wiring layer of a plurality of metal wiring layers, wherein the first conductor is coupled to a first terminal;

a second conductor formed on an upper metal wiring layer of the plurality of metal wiring layers; and

a plurality of parallel wires partitioned into a plurality of groups, wherein parallel wires included in each group of the plurality of groups are formed on a respective one of a subset of the plurality of metal wiring layers, wherein the subset of the plurality of metal wiring layers is between the upper metal wiring layer and the lower metal wiring layer,

wherein;

a first parallel wire and a second parallel wire of each group of the plurality of groups is coupled to a second terminal;

a third parallel wire of each group of the plurality of groups is coupled to the first conductor, wherein the third parallel wire is adjacent to the first parallel wire;

a fourth parallel wire of each group of the plurality of groups is coupled to the second conductor, wherein the fourth parallel wire is adjacent to the second parallel wire;

a fifth parallel wire of each group of a first subset of the plurality groups is coupled to the second conductor, and wherein the fifth parallel wire of each group of a second subset of the plurality of groups is coupled to the first conductor; and

the fifth parallel wire of each group of the plurality of groups is adjacent to the first parallel wire and the second parallel wire;

a control circuit coupled to the first terminal of each capacitor of the plurality of capacitors; and

a comparator coupled to the second terminal of each capacitor of the plurality of capacitors.

15. The system of claim 14, wherein the control circuit is configured to switch a coupling of the first terminal of a given capacitor of the plurality of capacitors between an input voltage signal, a reference voltage signal, and a ground signal.

16. The system of claim 15, wherein the control circuit is further configured to determine a voltage level of the input voltage signal dependent upon an output of the comparator.

17. The system of claim 14, wherein the first subset of the plurality of groups is mutually exclusive to the second subset of the plurality of groups.

18. The system of claim 17, wherein a number of groups included in the first subset of the plurality of groups is equal to a number of groups included in the second subset of the plurality of groups.

19. The system of claim 14, wherein an edge of the third parallel wire included in a given group of the plurality of groups is aligned to an edge of the third parallel wire included in any other given group of the plurality of groups.

20. The system of claim 14, wherein the second conductor is coupled to a third terminal, and wherein the third terminal is coupled to a ground signal.