Display Panel

• US 20150269910A1
• Filed: 06/13/2014
• Published: 09/24/2015
• Est. Priority Date: 03/21/2014
• Status: Active Grant

• Current Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Original Assignee: Chunghwa Picture Tubes Limited (Tatung Co., Ltd.)
• Inventors: Liao, Tzu-Chiang, Lai, Chih-Wen
• Granted Patent: US 9,280,953 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0421 Structural details of the set of electrodes
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/065 Waveforms comprising zero voltage phase or pause
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A display panel includes a plurality of rows of pixels, a gate driving circuit, and an inspection circuit. The gate driving circuit includes a plurality of gate driving units. The inspection circuit includes a plurality of transistors. Each transistor includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor is coupled to a contact pad. The control terminal of the transistor is coupled to the corresponding gate driving unit and a corresponding row of pixels. The second terminal of the transistor is coupled to the control terminal of the transistor.

Claims

1. A display panel comprising:

a plurality of rows of pixels, each row of pixels including a plurality of pixels;

a first gate driving circuit including a plurality of first gate driving units, each first gate driving unit outputting a first scan signal for driving a row of pixels coupled to the first gate driving unit;

a second gate driving circuit including a plurality of second gate driving units, each second gate driving unit outputting a second scan signal for driving a row of pixels coupled to the second gate driving unit;

a source driving circuit coupled to the plurality of pixels for transmitting data signals to the plurality of pixels;

a first inspection circuit including a plurality of first transistors, each first transistor including;

a first terminal coupled to a first test pad;

a control terminal coupled to a corresponding first gate driving unit; and

a second terminal coupled to the control terminal of the first transistor; and

a second inspection circuit, including a plurality of second transistors, each second transistor including;

a first terminal coupled to a second test pad;

a control terminal coupled to a corresponding second gate driving unit; and

a second terminal coupled to the control terminal of the second transistor;

wherein when the first gate driving unit outputs the first scan signal, the first scan signal enables the first transistor so as to transmit the first scan signal to the first test pad while the first transistor is enabled, and when the second gate driving unit outputs the second scan signal, the second scan signal enables the second transistor so as to transmit the second scan signal to the second test pad while the second transistor is enabled for determining whether the first gate driving unit and the second gate driving unit are able to output the first scan signal and the second scan signal correctly.

2. The display panel of claim 1 wherein the plurality of first transistors and the plurality of second transistors are N-type metal-oxide-semiconductor transistors.

3. The display panel of claim 1 wherein the plurality of first gate driving units are coupled to odd rows of pixels of the plurality of rows of pixels.

4. The display panel of claim 3 wherein the plurality of second gate driving units are coupled to even rows of pixels of the plurality of rows of pixels.

5. The display panel of claim 1 wherein the plurality of second gate driving units are coupled to even rows of pixels of the plurality of rows of pixels.

6. The display panel of claim 1 wherein the first gate driving circuit is disposed at a left side of the plurality of rows of pixels and the second gate driving circuit is disposed at a right side of the plurality of rows of pixels.

7. The display panel of claim 1 wherein the first gate driving circuit is disposed at a right side of the plurality of rows of pixels and the second gate driving circuit is disposed at a left side of the plurality of rows of pixels.

8. The display panel of claim 1 wherein the first inspection circuit is disposed between the first gate driving circuit and the plurality of rows of pixels.

9. The display panel of claim 8 wherein the second inspection circuit is disposed between the second gate driving circuit and the plurality of rows of pixels.

10. The display panel of claim 1 wherein the second inspection circuit is disposed between the second gate driving circuit and the plurality of rows of pixels.

11. A display panel comprising:

a plurality of rows of pixels, each row of pixels including a plurality of pixels;

a gate driving circuit including a plurality of gate driving units, each gate driving unit outputting a scan signal for driving a row of pixels coupled to the gate driving unit;

a source driving circuit coupled to the plurality of pixels for transmitting data signals to the plurality of pixels; and

an inspection circuit including a plurality of transistors, each transistor including;

a first terminal coupled to a test pad;

a control terminal coupled to a corresponding gate driving unit and a corresponding row of pixels; and

a second terminal coupled to the control terminal of the transistor;

wherein when the gate driving unit outputs the scan signal, the scan signal enables the transistor so as to transmit the scan signal to the test pad for determining whether the gate driving unit is able to output the scan signal correctly.

12. The display panel of claim 11 wherein the plurality of transistors are N-type metal-oxide-semiconductor transistors.

13. The display panel of claim 11 wherein a falling edge of a scan signal leads a rising edge of a following scan signal by a positive time interval.

14. The display panel of claim 13 wherein the positive time interval is greater than a resistor-capacitor delay (RC delay) of the gate driving unit.

15. The display panel of claim 11, wherein the inspection circuit is disposed between the gate driving circuit and the plurality of rows of pixels.