MEMORY MAPPING

• US 20150270015A1
• Filed: 03/19/2014
• Published: 09/24/2015
• Est. Priority Date: 03/19/2014
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Murphy, Richard C., Manning, Troy A.
• Application Number:
  US14/219,639
• Publication Number:
  US 20150270015A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

The present disclosure includes apparatuses, electronic device readable media, and methods for memory mapping. One example method can include testing a memory identifier against an indication corresponding to a set of mapped memory identifiers, and determining a memory location corresponding to the memory identifier responsive to testing.

Claims

1. A method for memory mapping, comprising:

testing a memory identifier against an indication corresponding to a set of mapped memory identifiers to determine to which memory mapping the memory identifier is presently subject; and

determining a memory location corresponding to the memory identifier responsive to testing.

2. The method of claim 1, wherein testing the memory identifier against the indication corresponding to the set of mapped memory identifiers to determine to which memory mapping the memory identifier is presently subject comprises testing to determine if the memory identifier may have been remapped from another memory mapping.

3. The method of claim 1, wherein testing the memory identifier against the indication corresponding to the set of mapped memory identifiers to determine to which memory mapping the memory identifier is presently subject comprises testing to determine whether the memory identifier may be subject to an alternative memory mapping.

4. The method of claim 3, wherein determining the memory location corresponding to the memory identifier responsive to testing comprises determining the memory location corresponding to the memory identifier using another memory mapping responsive to determining that the memory identifier is not subject to the alternative mapping.

5. The method of claim 3, wherein determining the memory location corresponding to the memory identifier responsive to testing comprises determining the memory location corresponding to the memory identifier responsive to testing using the alternative mapping responsive to determining that the memory identifier is subject to the alternative mapping.

6. The method of claim 1, wherein testing a memory identifier against an indication corresponding to a set of mapped memory identifiers to determine to which memory mapping the memory identifier is presently subject comprises testing the memory identifier to dynamically select between memory mappings.

7. The method of claim 1, wherein the memory identifier is subject to a first memory mapping under a first condition and is subject to a second memory mapping under a second condition.

8. The method of claim 1, wherein determining the memory location includes:

determining the memory location corresponding to the memory identifier according to a first mapping responsive to the testing indicating that the memory identifier is not included in the set of mapped memory identifiers; and

determining the memory location corresponding to the memory identifier according to a second mapping responsive to the testing indicating that the memory identifier is included in the set of mapped memory identifiers.

9. The method of claim 8, wherein determining the memory location corresponding to the memory identifier according to the second mapping includes looking-up a memory location corresponding to the memory identifier in an associative data structure.

10. The method of claim 9, wherein the associative data structure is a data table indexed by the memory identifier.

11. The method of claim 8, wherein determining the memory location corresponding to the memory identifier according to the second mapping includes deterministically mapping the memory identifier to a physical memory location.

12. The method of claim 1, wherein testing the memory identifier against the indication corresponding to the set of mapped memory identifiers includes testing the memory identifier using a memory identifier filter.

13. The method of claim 12, wherein the memory identifier filter is configured to provide the indication such that false negatives are not permitted, a false negative being an indication of the memory identifier not being included in the set of mapped memory identifiers when it actually is in the set of mapped memory identifiers.

14. The method of claim 12, wherein the memory identifier filter is configured to utilize a number of different hash functions that hashes a member of the set of mapped memory identifiers to a respective filter array position.

15. The method of claim 14, wherein testing the memory identifier using a memory identifier filter includes testing the memory identifier using a Bloom filter.

16. The method of claim 14, wherein testing the memory identifier using a memory identifier filter includes testing the memory identifier using a skip list.

17. A method for memory mapping, comprising:

determining with a filter whether a memory identifier may be mapped according to an alternative memory mapping; and

determining a memory location corresponding to the memory identifier according to another memory mapping responsive to determining the memory identifier is not mapped according to the alternative memory mapping.

18. The method of claim 17, wherein determining with the filter comprises determining with a Bloom filter.

19. The method of claim 17, wherein determining with a filter comprises determining with a skip list.

20. The method of claim 17, further comprising:

determining with the filter whether another second memory identifier may be mapped according to the alternative memory mapping; and

determining another memory location corresponding to the other memory identifier according to the alternative memory mapping responsive to determining the other memory identifier may be mapped according to the alternative memory mapping.

21. The method of claim 17, further comprising:

determining with the filter whether another memory identifier may be mapped according to the alternative memory mapping; and

determining another memory location corresponding to the other memory identifier according to the other memory mapping responsive to determining the other memory identifier is not mapped according to the alternative memory mapping.

22. The method of claim 17, further comprising:

determining with the filter whether another memory identifier may be mapped according to the alternative memory mapping;

determining another memory location corresponding to the other memory identifier according to the other memory mapping responsive to determining the other memory identifier is not mapped according to the alternative memory mapping;

remapping the other memory identifier according to the alternative memory mapping responsive to determining the other memory location is failed; and

re-tuning the filter to indicate that the other memory identifier is mapped according to the alternative memory mapping.

23. The method of claim 17, further comprising:

determining with the filter whether another memory identifier may be mapped according to the alternative memory mapping;

determining whether the other memory identifier is mapped according to the alternative memory mapping responsive to determining that the other memory identifier may be mapped according to the alternative memory mapping; and

determining another memory location corresponding to the other memory identifier according to the other memory mapping responsive to determining the other memory identifier is not mapped according to the alternative memory mapping.

24. The method of claim 17, wherein the other memory mapping comprises a previous memory mapping and the alternative memory mapping comprises a subsequent memory mapping.

25. The method of claim 17, wherein the other memory mapping comprises a default memory mapping.

26. The method of claim 17, wherein the other memory mapping comprises a primary memory mapping and the alternative memory mapping comprises a secondary memory mapping.

27. A method for memory mapping, comprising:

testing a memory identifier for exclusion from a group of memory identifiers; and

selecting a memory mapping from among a plurality of memory mappings responsive to testing the memory identifier for exclusion from the group of memory identifiers.

28. The method of claim 27, wherein selecting the memory mapping includes selecting a first memory mapping when the memory identifier tests as excluded from the group of memory identifiers and selecting a second memory mapping when the memory identifier tests as not excluded from the group of memory identifiers.

29. The method of claim 27, wherein selecting the memory mapping includes selecting an associative data structure memory mapping mechanism when the memory identifier tests as excluded from the group of memory identifiers and selecting a deterministic memory mapping mechanism when the memory identifier tests as not excluded from the group of memory identifiers.

30. The method of claim 27, wherein selecting the deterministic memory mapping mechanism includes computing a memory location based on data comprising the memory identifier.

31. The method of claim 27, wherein selecting the memory mapping includes selecting a first associative data structure memory mapping mechanism when the memory identifier tests as excluded from the group of memory identifiers and selecting a second associative data structure memory mapping mechanism when the memory identifier tests as not excluded from the group of memory identifiers.

32. The method of claim 27, further comprising testing each memory identifier for exclusion from the group of memory identifiers.

33. The method of claim 27, further comprising determining a memory location corresponding to the memory identifier according to the selected memory mapping.

34. The method of claim 27, wherein:

testing the memory identifier for exclusion from the group of memory identifiers comprises testing the memory identifier for exclusion from a plurality of groups of memory identifiers,

wherein selecting the memory mapping comprises selecting the memory mapping from among the plurality of memory mappings responsive to testing the memory identifier for exclusion from the plurality of groups of memory identifiers, and

wherein testing utilizes a plurality of filters.

35. An apparatus, comprising:

memory; and

a memory mapping module configured to;

test a memory identifier for exclusion from a group of mapped memory identifiers; and

determine a memory location corresponding to the memory identifier responsive to the test of the memory identifier.

36. The apparatus of claim 35, further comprising a processing resource and an interface between the memory and the processing resource, wherein the memory mapping module is included in the interface.

37. The apparatus of claim 35, wherein the memory comprises a memory device wherein the memory mapping module is associated with the memory device.

38. The apparatus of claim 35, further comprising a host, and wherein the memory comprises a memory array and the memory mapping module is between the host and the memory array.

39. The apparatus of claim 38, wherein the memory mapping module is at the host.

40. The apparatus of claim 38, wherein the memory mapping module is in control circuitry configured to control operations performed on the memory array.

41. The apparatus of claim 38, wherein the memory mapping module is in address circuitry coupled to the memory array.

42. The apparatus of claim 35, wherein the memory mapping module includes a filter configured to select a memory mapping from among a plurality of memory mappings, the selected memory mapping being configured to determine the memory location corresponding to the memory identifier.

43. The apparatus of claim 35, wherein the filter is configured to provide no false negative results with respect to inclusion of the memory identifier in the group of mapped memory identifiers.

44. The apparatus of claim 35, wherein the filter is a Bloom filter.

45. The apparatus of claim 35, wherein the filter is a skip list.

46. The apparatus of claim 35, wherein the group of mapped memory identifiers is a group of remapped memory identifiers, and the memory mapping module is configured to determine the memory location from an associative data structure where the memory identifier is excluded from the group of remapped memory identifiers and further configured to determine the memory location from a different associative data structure where the memory identifier is not excluded from the group of remapped memory identifiers.

47. The apparatus of claim 35, wherein the group of mapped memory identifiers is a group of remapped memory identifiers, and the memory mapping module is configured to determine the memory location from an associative data structure where the memory identifier is excluded from the group of remapped memory identifiers and further configured to compute the memory location from the memory identifier where the memory identifier is not excluded from the group of remapped memory identifiers.

48. The apparatus of claim 35, wherein the apparatus comprises a hybrid memory cube (HMC).

49. A non-transitory electronic device readable medium storing a set of instructions executable by an electronic device to:

test a memory identifier for exclusion from a group of memory identifiers; and

select a memory mapping from among a plurality of memory mappings responsive to testing the memory identifier.

50. The medium of claim 49, wherein the set of instructions is executable by an electronic device to:

test the memory identifier for exclusion from a group of mapped memory identifiers; and

select an alternate memory mapping responsive to the memory identifier not being excluded from the group of mapped memory identifiers.