Method of Semiconductor Integrated Circuit Fabrication

• US 20150270170A1
• Filed: 06/08/2015
• Published: 09/24/2015
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Ching-Fu, Peng, Chao-Hsien, Wu, Hsien-Chang, Lee, Hsiang-Huan
• Granted Patent: US 9,570,347 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Claims

1. A method comprising:

forming a conductive layer on a semiconductor substrate;

forming a patterned material layer on the conductive layer;

forming a catalyst layer on the conductive layer;

forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and

removing the conductive layer by using the CNTs as a mask to form conductive features.

2. The method of claim 1, wherein forming the patterned material layer on the conductive layer includes:

forming a photosensitive layer directly on the conductive layer; and

patterning the photosensitive layer, wherein the patterned photosensitive layer includes an opening exposing a portion of the conductive layer.

3. The method of claim 2, wherein forming the catalyst layer on the conductive layer includes forming the catalyst layer within the opening of the patterned photosensitive layer and directly on the exposed portion of the conductive layer.

4. The method of claim 1, wherein the catalyst layer only partially fills the opening.

5. The method of claim 1, removing the material layer prior to forming the plurality of carbon nanotubes (CNTs) from the catalyst layer.

6. The method of claim 5, wherein removing the material layer includes completely removing the material layer to expose portions of the conductive layer.

7. The method of claim 1, further comprising forming another patterned material layer on the conductive layer prior to forming the patterned material layer on the conductive layer such that the patterned material layer is disposed directly over at least a portion of the another patterned material layer.

8. The method of claim 7, wherein etching the conductive layer by using the CNTs as the etching mask to form metal features includes removing the conductive layer by using the CNTs and the another material layer as the mask.

9. A method comprising:

forming a conductive layer on a semiconductor substrate;

forming a patterned hard mask layer directly on the conductive layer;

forming a patterned photosensitive layer directly on the patterned hard mask layer;

forming a catalyst layer directly on the conductive layer;

forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and

removing the conductive layer by using the CNTs as a mask to form conductive features.

10. The method of claim 9, wherein forming the patterned photosensitive layer directly on the patterned hard mask layer further includes forming the patterned photosensitive layer directly on the conductive layer.

11. The method of claim 9, wherein the patterned photosensitive layer includes an opening, and

wherein forming the catalyst layer directly on the conductive layer includes forming the catalyst layer in the opening of the patterned photosensitive layer such that the catalyst layer physically contacts the patterned photosensitive layer.

12. The method of claim 9, further comprising completely removing the patterned photosensitive layer prior to forming the plurality of CNTs from the catalyst layer.

13. The method of claim 9, wherein the catalyst layer includes a metal selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni) and molybdenum (Mo).

14. The method of claim 9, further comprising forming an interlayer dielectric layer over the patterned hard mask layer after removing the conductive layer by using the CNTs as the mask to form conductive features.

15. A method comprising:

forming a metal layer on a semiconductor substrate;

forming a patterned hard mask layer directly on the metal layer;

forming a patterned photosensitive layer directly on the patterned hard mask layer;

forming a catalyst layer directly on the metal layer through the patterned photosensitive layer and the patterned hard mask layer;

forming a plurality of carbon nanotubes (CNTs) from the catalyst layer; and

etching the metal layer by using the CNTs as a mask.

16. The method of claim 15, wherein etching the metal layer by using the CNTs as the mask includes performing a dry etching process.

17. The method of claim 15, further comprising removing the patterned photosensitive layer prior to forming the plurality of CNTs from the catalyst layer.

18. The method of claim 15, wherein forming the plurality of CNTs from the catalyst layer includes heating the catalyst layer and the substrate to about 700°

C. and providing at least one gas selected from the group consisting of ammonia gas, nitrogen gas, and hydrogen gas.

19. The method of claim 15, wherein forming the patterned photosensitive layer directly on the patterned hard mask layer further includes forming the patterned photosensitive layer directly on the metal layer.

20. The method of claim 15, wherein etching the metal layer by using the CNTs as the mask forms a conductive feature that is part of an interconnect structure of a device.