SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME

• US 20150270196A1
• Filed: 06/03/2015
• Published: 09/24/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Arbuthnot, Roger M., St. Germain, Stephen
• Granted Patent: US 9,397,028 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04034 Bonding areas specifically adapted for strap connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32258 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37012 Cross-sectional shape
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40499 : Material of the auxiliary connecting means
• CPC Class Codes: H01L 2224/4103 : Connectors having different sizes
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73263 : Layer and strap connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 2224/84385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/492 : Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/67 : of a plurality of connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In one embodiment, methods for making semiconductor devices are disclosed.

Claims

1. A semiconductor device comprising:

a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate and second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate; and

a semiconductor die comprising a first contact pad electrically coupled to the conductive substrate, wherein the first contact pad is soldered to both the first planar surface of the first elevated region and the second planar surface of the second elevated region, and wherein the first planar surface of the first elevated region has different dimensions than the second planar surface of the second elevated region.

2. The semiconductor device of claim 1, wherein the conductive substrate comprises at least 10 elevated regions.

3. The semiconductor device of claim 2, wherein a number of the elevated regions on the first side of the conductive substrate is greater than a number of the elevated regions on the first side of the conductive substrate soldered to the semiconductor die.

4. The semiconductor device of claim 1, wherein the conductive substrate and the semiconductor die are at least partially encapsulated in a molding material.

5. The semiconductor device of claim 4, wherein the molding material is disposed between the first elevated region and the second elevated region.

6. The semiconductor device of claim 1, wherein the first planar surface of the first elevated region has a first corner that is laterally aligned with a first corner of the first contact pad.

7. The semiconductor device of claim 6, wherein the second planar surface of the second elevated region has a second corner that is laterally aligned with a second corner of the first contact pad.

8. The semiconductor device of claim 6, wherein the first planar surface of the first elevated region has a second corner that is laterally aligned with a second corner of the first contact pad.

9. The semiconductor device of claim 1, wherein the conductive substrate further comprises a third elevated region on the first side of the conductive substrate, wherein the third elevated comprises a third planar surface on the first side of the conductive substrate, and wherein the first contact pad is soldered to the third planar surface of the third elevated region.

10. The semiconductor device of claim 9, wherein the first planar surface of the first elevated region has a first corner that is laterally aligned with a first corner of the first contact pad, wherein the second planar surface of the second elevated region has a second corner that is laterally aligned with a second corner of the first contact pad, and wherein the third planar surface of the third elevated region has a third corner that is laterally aligned with a third corner of the first contact pad.

11. The semiconductor device of claim 1, wherein only a portion of the first planar surface of the first elevated region is soldered to the first contact pad.

12. A semiconductor device comprising:

a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region on a first side of the conductive substrate, a second elevated region on the first side of the conductive substrate, and a third elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate, and wherein the third elevated region comprises a third planar surface on the first side of the conductive substrate; and

a semiconductor die comprising a first contact pad and a second contact pad electrically coupled to the conductive substrate, wherein the first contact pad is soldered to the first planar surface of the first elevated region and the second contact pad is soldered to the second planar surface of the second elevated region, and wherein the third planar surface of the third elevated region is not soldered to the semiconductor die.

13. The semiconductor device of claim 12, wherein the third planar surface of the third elevated region is laterally positioned away from a footprint of the semiconductor die.

14. The semiconductor device of claim 13, wherein the conductive substrate further comprises a fourth elevated region on the first side of the conductive substrate, wherein the fourth elevated region comprises a fourth planar surface on the first side of the conductive substrate, and wherein fourth elevated region is laterally positioned away from the footprint of the semiconductor die.

15. The semiconductor device of claim 12, wherein the conductive substrate and the semiconductor die are at least partially encapsulated in a molding material.

16. The semiconductor device of claim 15, wherein the molding material is disposed between the first elevated region and the second elevated region.

17. The semiconductor device of claim 12, wherein the first planar surface of the first elevated region has a first corner that is laterally aligned with a first corner of the first contact pad.

18. The semiconductor device of claim 17, wherein the second planar surface of the second elevated region has a second corner that is laterally aligned with a first corner of the second contact pad.

19. The semiconductor device of claim 17, wherein the first planar surface of the first elevated region has a second corner that is laterally aligned with a second corner of the first contact pad.

20. The semiconductor device of claim 12, wherein the first planar surface of the first elevated region has different dimensions than the second planar surface of the second elevated region.