SHALLOW TRENCH ISOLATION FOR END FIN VARIATION CONTROL

• US 20150270264A1
• Filed: 06/08/2015
• Published: 09/24/2015
• Est. Priority Date: 03/24/2014
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Basker, Veeraraghavan S., Liu, Zuoguang, Yamashita, Tenko, Yeh, Chun-Chen
• Granted Patent: US 9,412,643 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of fabricating a fin field effect transistor (FinFET) device and the device are described. The method includes forming a deep STI region adjacent to a first side of an end fin among a plurality of fins and lining the deep STI region, including the first side of the end fin, with a passivation layer. The method also includes depositing an STI oxide into the deep STI region, the passivation layer separating the STI oxide and the first side of the end fin, etching back the passivation layer separating the STI oxide and the first side of the end fin to a specified depth to create a gap, and depositing gate material, the gate material covering the gap.

Claims

1. A fin field effect transistor (FinFET) device, comprising:

a plurality of fins;

a plurality of shallow trench isolation (STI) regions, each adjacent pair of the plurality of fins being separated by one of the plurality of STI regions;

a deep STI region formed on a first side of an end fin among the plurality of fins; and

gate material deposited over the plurality of fins and in the deep STI region, the gate material covering both sides of a fin reveal of each of the plurality of fins and covering the first side of the end fin by filling a gap between the first side of the end fin and a gate oxide layer in the deep STI region.

2. The device according to claim 1, wherein a depth of the gap is based on an etch back of a passivation layer lining the deep STI region.

3. The device according to claim 2, wherein the passivation layer is silicon nitride (SiN).

4. The device according to claim 2, wherein the passivation layer lining the deep STI region is a redeposition of the passivation layer removed during an etch of the deep STI region.

5. The device according to claim 2, wherein the depth of the gap is specified to result in an equal fin reveal of the end fin on the first side and a second side opposite to the first side.

6. The device according to claim 5, wherein a channel width on the first side of the end fin and channel widths between each pair of fins is a same.

7. The device according to claim 1, wherein the gate material is a polysilicon.

8. The device according to claim 1, wherein the plurality of fins are spaced apart at a specified interval based on a plurality of spacers used to form the plurality of fins.

9. The device according to claim 8, wherein the plurality of spacers comprise silicon dioxide (SiO₂).

10. The device according to claim 8, wherein the plurality of spacers are shaped using an amorphous silicon (a-Si) mandrel.