VERTICAL NITRIDE SEMICONDUCTOR DEVICE

• US 20150270356A1
• Filed: 03/19/2015
• Published: 09/24/2015
• Est. Priority Date: 03/20/2014
• Status: Active Application

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Palacios, Tomas Apostol, Zhang, Yuhao
• Application Number:
  US14/662,837
• Publication Number:
  US 20150270356A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66204 Diodes
• CPC Class Codes: H01L 29/66212 Schottky diodes
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7788 Vertical transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A vertical semiconductor device and a method of forming the same. A vertical semiconductor device has a substrate that includes a first material, a first electrode below the substrate, and at least one semiconductor region. The at least one semiconductor region includes a second material different from the first material. The second material is a III-nitride semiconductor material. The at least one semiconductor region is formed over the substrate. The vertical semiconductor device also has a second electrode over the at least one semiconductor region.

Claims

1. A vertical semiconductor device, comprising:

a substrate comprising a first material;

a first electrode below the substrate;

at least one semiconductor region comprising a second material different from the first material, the second material being a III-nitride semiconductor material, the at least one semiconductor region being formed over the substrate; and

a second electrode over the at least one semiconductor region.

2. The vertical semiconductor device of claim 1, wherein the second material is lattice-mismatched with respect to the first material.

3. The vertical semiconductor device of claim 2, wherein the vertical semiconductor device comprises a buffer region between the substrate and the at least one semiconductor region that buffers a lattice mismatch between the first material and the second material.

4. The vertical semiconductor device of claim 3, wherein the buffer region is compositionally graded or has a superlattice structure.

5. The vertical semiconductor device of claim 3, wherein the buffer region comprises a III-nitride semiconductor material.

6. The vertical semiconductor device of claim 1, wherein the at least one semiconductor region comprises a plurality of semiconductor regions.

7. The vertical semiconductor device of claim 6, wherein the plurality of semiconductor regions comprises a first semiconductor region comprising a III-nitride semiconductor material and a second semiconductor region comprising a III-nitride semiconductor material.

8. The vertical semiconductor device of claim 7, wherein the first semiconductor region has a higher conductivity than that of the second semiconductor region.

9. The vertical semiconductor device of claim 8, wherein the first semiconductor region contacts the first electrode.

10. The vertical semiconductor device of claim 8, wherein the second semiconductor region comprises a drift region.

11. The vertical semiconductor device of claim 1, wherein the III-nitride semiconductor material comprises a gallium nitride semiconductor material.

12. The vertical semiconductor device of claim 1, wherein the substrate comprises a compound semiconductor material, a group IV semiconductor material, an oxide material, graphene or sapphire.

13. The vertical semiconductor device of claim 12, wherein the substrate comprises a semiconductor material that is lattice mismatched with respect to the III-nitride semiconductor material.

14. The vertical semiconductor device of claim 13, wherein the semiconductor material comprises an aluminum nitride semiconductor material.

15. The vertical semiconductor device of claim 1, further comprising a trench formed in the substrate.

16. The vertical semiconductor device of claim 15, wherein the first electrode is disposed in the trench.

17. The vertical semiconductor device of claim 16, further comprising a thermally conductive fill material in the trench.

18. The vertical semiconductor device of claim 16, wherein the vertical semiconductor device comprises a buffer region between the substrate and the at least one semiconductor region.

19. The vertical semiconductor device of claim 18, wherein the trench is further formed in the buffer region and the first electrode contacts the at least one semiconductor region in the trench.

20. The vertical semiconductor device of claim 19, wherein the buffer region is electrically insulating, the substrate is electrically insulating or both the buffer region and the substrate are electrically insulating.

21. The vertical semiconductor device of claim 18, wherein the buffer region is electrically conductive and the first electrode contacts the buffer region in the trench.

22. The vertical semiconductor device of claim 21, wherein a bottom of the buffer region is doped to form an ohmic contact with the first electrode

23. The vertical semiconductor device of claim 21, wherein the substrate is electrically insulating.

24. The vertical semiconductor device of claim 1, wherein the vertical semiconductor device comprises a buffer region between the substrate and the at least one semiconductor region, wherein the buffer region is electrically conductive and the substrate is electrically conductive.

25. The vertical semiconductor device of claim 1, wherein the vertical semiconductor device comprises a diode or a transistor.

26. A method of forming a vertical semiconductor device, the method comprising:

forming, over a substrate comprising a first material, at least one semiconductor region comprising a second material different from the first material, the second material being a III-nitride semiconductor material; and

forming a first electrode on a first side of the substrate and a second electrode over the at least one semiconductor region on a second side of the substrate.

27. The method of claim 26, further comprising forming a buffer region over the substrate and below the at least one semiconductor region, wherein the at least one semiconductor region is formed over the buffer layer.

28. The method of claim 27, further comprising thinning the substrate.

29. The method of claim 28, further comprising forming a trench in the substrate, wherein the first electrode is formed in the trench.

30. The method of claim 29, further comprising filling the trench with a thermally conductive material.

31. The method of claim 28, wherein the trench is further formed in the buffer region.

32. The method of claim 27, further comprising doping the buffer region.