INTEGRATED CIRCUIT CAPACITORS FOR ANALOG MICROCIRCUITS
First Claim
1. An integrated circuit capacitor, comprising:
- a silicon-on-insulator substrate including a buried oxide layer over a doped region;
a dual gate field effect transistor formed on the substrate, the dual gate field effect transistor having a primary gate and a secondary gate; and
a contact to the doped region, for use as the secondary gate of the dual gate field effect transistor.
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Accused Products
Abstract
Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.
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Citations
21 Claims
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1. An integrated circuit capacitor, comprising:
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a silicon-on-insulator substrate including a buried oxide layer over a doped region; a dual gate field effect transistor formed on the substrate, the dual gate field effect transistor having a primary gate and a secondary gate; and a contact to the doped region, for use as the secondary gate of the dual gate field effect transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of making an integrated circuit capacitor, the method comprising:
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providing a silicon-on-insulator substrate including a buried oxide layer over a doped region; forming a field effect transistor on the substrate, the field effect transistor including source and drain regions that have substantially vertical profiles; and forming a front side contact to the doped region.
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10. A microcircuit, comprising:
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a voltage supply; an operational amplifier electrically coupled to the voltage supply, the operational amplifier having inverting and non-inverting input terminals and an output terminal; and a capacitive PMOS field effect transistor coupled to the operational amplifier, the transistor including a doped substrate, and a buried oxide layer within the doped substrate. - View Dependent Claims (11, 12, 13)
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14. A microcircuit, comprising:
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a first stage that receives an input signal at an input frequency; a second stage that produces an output signal at an output frequency, the output signal coupled to the first stage; and a third stage including a pair of capacitors in the form of dual gate transistors, the third stage coupled between the first and second stages. - View Dependent Claims (15, 16, 17)
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18. A method, comprising:
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coupling a supply voltage to source and drain terminals of a dual gate PMOS transistor formed on a doped substrate that contains a buried oxide layer; applying a bias voltage to a primary gate of the dual gate PMOS transistor to control current in a channel region between the source and drain terminals; grounding the doped substrate via a secondary gate; and operating the dual gate PMOS transistor as an integrated capacitor for use in analog microcircuits. - View Dependent Claims (19)
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20. A method, comprising:
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grounding source and drain terminals of a dual gate NMOS transistor formed on a doped substrate that contains a buried oxide layer; coupling a supply voltage to the doped substrate via a secondary gate; applying a bias voltage to a primary gate of the dual gate NMOS transistor to control current in a channel region between the source and drain terminals; and operating the dual gate NMOS transistor as an integrated capacitor for use in analog microcircuits. - View Dependent Claims (21)
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Specification