Clock and data recovery circuit using an injection locked oscillator

• US 20150270943A1
• Filed: 03/16/2015
• Published: 09/24/2015
• Est. Priority Date: 03/24/2014
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Liu, Shiue-Shin, Hung, Chih-Chien, Lin, Shao-Hung
• Granted Patent: US 9,432,178 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate

Abstract

A clock and data recovery circuit includes a sampler, a skew compensation block, a pulse generator, and an injection locked oscillator. The injection locked oscillator generates a recovered clock signal, the pulse generator generates a pulse signal according to input data for controlling the injection locked oscillator, the skew compensation block compensates the input data and generate compensated data, and the sampler samples the compensated data according to the recovered clock signal.

Claims

1. A clock and data recovery circuit, comprising:

an injection locked oscillator configured to generate a recovered clock signal, the injection locked oscillator comprising;

a two stage ring oscillator; and

an injection switch coupled to the two stage ring oscillator;

a pulse generator coupled to the injection locked oscillator and configured to generate a pulse signal according to input data for controlling the injection locked oscillator; and

a sampler coupled to the input data and the injection locked oscillator and configured to sample the input data according to the recovered clock signal.

2. The circuit of claim 1, further comprising:

a skew compensation block coupled to the input data and configured to compensate the input data and generate compensated data to be sampled by the sampler.

3. The circuit of claim 1, where the ring oscillator operates at half of an incoming data rate.

4. The circuit of claim 1, further comprising:

a frequency locked loop coupled to the injection locked oscillator and configured to correct a frequency error in the injection locked oscillator.

5. The circuit of claim 4, wherein the frequency locked loop comprises:

a sample and hold circuit coupled to the pulse generator and the injection locked oscillator and configured to sample a voltage of an injection terminal of the injection locked oscillator and store the voltage in a hold capacitor according to an even cycle or an odd cycle of the injection locked oscillator; and

a loop filter configured to receive a voltage from the sample and hold circuit and generate a control voltage to control the injection lock oscillator;

the loop filter further controls the bandwidth of the frequency locked loop such that the bandwidth of the frequency locked loop is low enough to avoid disturbing injection locking of the clock and data recovery circuit.

6. The circuit of claim 1, further comprising:

a delay locked loop coupled to the injection locked oscillator and configured to find an optimal sampling point of the recovered data;

wherein bandwidth of the delay locked loop is low enough to avoid disturbing injection locking of the clock and data recovery circuit.

7. The circuit of claim 1, wherein the two stage ring oscillator comprises:

a first oscillator stage having a first input terminal, a second input terminal, a first output terminal, and a second output terminal; and

a second oscillator stage having a first input terminal coupled to the first output terminal of the first oscillator stage, a second input terminal coupled to the second output terminal of the first oscillator stage, a first output terminal coupled to the second input terminal of the first oscillator stage, and a second output terminal coupled to the first input terminal of the first oscillator stage.

8. The circuit of claim 7, wherein each oscillator stage of the two stage ring oscillator comprises:

a first delay cell having an input terminal and an output terminal;

a second delay cell having an input terminal and an output terminal;

a third delay cell having;

an input terminal coupled to the output terminal of the second delay cell; and

an output terminal coupled to the output terminal of the first delay cell; and

a fourth delay cell having;

an input terminal coupled to the output terminal of the first delay cell; and

an output terminal coupled to the output terminal of the second delay cell.

9. A method of operation of a clock and data recovery, comprising:

an injection locked oscillator generating a recovered clock signal;

a pulse generator generating a pulse signal according to input data for controlling the injection locked oscillator; and

a sampler sampling the input data according to the recovered clock signal.

10. The method of claim 9, further comprising:

a skew compensation block compensating the input data.

11. The method of claim 9, further comprising:

a frequency locked looped correcting a frequency error of the injection locked oscillator.

12. The method of claim 11, wherein the frequency locked looped correcting a frequency error of the injection locked oscillator comprises:

a sample and hold circuit sampling a frequency from the injection locked oscillator and storing the frequency in a hold capacitor of the sample and hold circuit; and

a loop filter receiving a voltage from the sample and hold circuit and generating a control voltage to control the injection lock oscillator.

13. The method of claim 9, further comprising:

a delay locked loop finding an optimal sampling point of the recovered data.

14. The method of claim 13, wherein the delay locked loop operates at a lower clock frequency than the injection locked oscillator.