System and Method for Low-Latency Network Data Switching

• US 20150271106A1
• Filed: 03/19/2014
• Published: 09/24/2015
• Est. Priority Date: 03/19/2014
• Status: Active Grant

• Current Assignee: Arista Networks, Inc.
• Original Assignee: xCelor LLC
• Inventors: Walker, Robert James, Gratzl, Stefan Josef, Sardaryan, Sergey, Sardaryan, Vahan
• Granted Patent: US 9,674,118 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04L 41/00 Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
• CPC Class Codes: H04L 45/28 using route fault recovery
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance

Abstract

A digital networking system includes a digital crosspoint switch, a host controller, and a data processing card that includes a programmable logic device such as a field-programmable gate array (FPGA). The host controller is operative to configure both the data processing card and the digital crosspoint switch in accordance with commands received over a user interface. The system is configurable to direct incoming data through the crosspoint switch to the data processing card for processing, and then back through the crosspoint switch for distribution to one or more network ports. The processing performed by the data processing card may include, among other options, feed filtering of a digital market data feed for use in high-frequency trading applications.

Claims

1. An apparatus comprising:

a digital crosspoint switch having a crosspoint control interface and a plurality of crosspoint ports, including a set of internal crosspoint ports and a set of external crosspoint ports;

a data processing card including a programmable logic device, wherein;

the data processing card includes a logic control interface and a plurality of data processing ports, including at least a first data processing input port and a first data processing output port,

each of the data processing ports is connected to a respective internal crosspoint port, and

the programmable logic device is configurable through the logic control interface and is operable to process data received on the first data processing input port and to output processed data on the first data processing output port; and

a host controller, connected to the crosspoint control interface and to the logic control interface, wherein the host controller includes a processor and a non-transitory computer-readable medium storing executable management instructions that, when executed on the processor, are operative to configure the digital crosspoint switch over the crosspoint control interface and to configure the data processing card over the logic control interface.

2. The apparatus of claim 1, wherein the programmable logic device is an FPGA.

3. The apparatus of claim 2, wherein the executable management instructions are further operative to direct the host controller to program the FPGA by sending FPGA program instructions over the logic control interface.

4. The apparatus of claim 2, further comprising a management network interface connected to the host controller, wherein the executable management instructions are further operative to retrieve FPGA program instructions over the management network interface and to program the FPGA by sending the FPGA program instructions over the logic control interface.

5. The apparatus of claim 1, wherein the executable management instructions are further operative:

to provide a user interface for receiving user commands; and

to configure the data processing card in accordance with the user commands.

6. The apparatus of claim 5, wherein the user interface is a command-line interface.

7. The apparatus of claim 1, further comprising a plurality of transceivers, each transceiver having an external transceiver interface and an internal transceiver interface, wherein each of the internal transceiver interfaces is connected to a respective external crosspoint port.

9. The apparatus of claim 7, wherein the external transceiver interfaces are of a type selected from the group consisting of SFP, SFP+, QSFP, and QSFP+.

10. The apparatus of claim 7, wherein the internal transceiver interfaces are of a type selected from the group consisting of SFI and XFI.

11. The apparatus of claim 1, wherein the host controller is connected to the crosspoint control interface through a USB connection.

12. The apparatus of claim 1, wherein the crosspoint control interface includes an I2C bus.

13. The apparatus of claim 1, wherein the logic control interface includes a PCI express bus.

14. The apparatus of claim 1, wherein the programmable logic device is programmed:

to receive, on the first data processing input port, a first network data packet including a market data message that includes a first security symbol;

to determine whether the first security symbol is a member of a first predetermined symbol group associated with the first data processing output port; and

to output the first network data packet on the first data processing output port only after determining that the first security symbol is a member of the first predetermined symbol group.

15. The apparatus of claim 1, wherein the programmable logic device is further programmed:

to determine whether the first security symbol is a member of a second predetermined symbol group associated with a second data processing output port; and

to output first network data packet on the second data processing output port only after determining that the first security symbol is a member of the second predetermined symbol group.

16. The apparatus of claim 1, wherein the programmable device is programmed to receive, on the first data processing input port, a plurality of network data packets, and to output, on the first data processing output port, only the network data packets that satisfy a predetermined filtering criterion.

17. A method comprising:

receiving, at a first port connected to a crosspoint switch, a digital market data feed comprising a plurality of packets;

directing the digital market data feed through the crosspoint switch to a second port connected to a data processing card that includes an FPGA;

processing the digital market data feed by the FPGA to generate at least a first processed market data feed;

directing the first processed market data feed to a third port connected to the crosspoint switch; and

operating the crosspoint switch to replicate the first processed market data feed to a first plurality of output ports.

18. The method of claim 17, wherein the processing of the market data feed includes identifying packets that meet a first predetermined filtering criterion, and wherein the first processed market data feed consists of the packets that meet the first predetermined filtering criterion.

19. The method of claim 18, wherein the processing of the market data feed includes identifying packets that meet a second predetermined filtering criterion, further comprising:

generating a second processed market data feed consisting of the packets that meet the second predetermined criterion;

directing the second processed market data feed to a fourth port connected to the crosspoint switch; and

operating the crosspoint switch to replicate the second processed market data feed to a second plurality of output ports.

20. The method of claim 17, wherein the processing of the market data feed includes:

receiving a first network data packet including a market data message that includes a first security symbol;

determining whether the first security symbol is a member of a first predetermined symbol group; and

including the first network data packet in the first processed market data feed only after determining that the first security symbol is a member of the first predetermined symbol group.

21. An apparatus comprising:

a digital crosspoint switch having a crosspoint control interface and a plurality of crosspoint ports, including a set of internal crosspoint ports and a set of external crosspoint ports;

a plurality of network interfaces connected to the external crosspoint ports;

a data processing card including a programmable logic device, wherein the data processing card includes a logic control interface, a first data processing port connected to a first internal crosspoint port, and a second data processing port connected to a second internal crosspoint port; and

a host controller connected to the crosspoint control interface and to the logic control interface, wherein the host controller includes a processor and a non-transitory computer-readable medium storing executable management instructions that, when executed on the processor, are operative;

to configure the digital crosspoint switch to replicate input data from a first one of the network interfaces to the first data processing port;

to configure the data processing card to process the input data and to generate first processed data on the second data processing port; and

to configure the digital crosspoint switch to replicate the first processed data from the second data processing port to at least a second one of the network interfaces.

22. The apparatus of claim 21, wherein the management instructions are operative to configure the digital crosspoint switch to replicate the first processed data from the second data processing port to a first plurality of the network interfaces.

23. The apparatus of claim 21, wherein the management instructions are operative to configure the data processing card:

to receive at the first data processing port a digital market data feed comprising a plurality of packets; and

to identify packets that meet a first predetermined filtering criterion;

wherein the first processed data consists of the packets that meet the first predetermined filtering criterion.

24. The apparatus of claim 21, wherein the programmable logic device is an FPGA.

25. The apparatus of claim 21, wherein the data processing card further comprises a third data processing port connected to a third internal crosspoint port, and wherein the management instructions are operative:

to configure the data processing card to process the input data and to generate second processed data on the third data processing port; and

to configure the digital crosspoint switch to replicate the second processed data from the third data processing port to at least a third one of the network interfaces.

26. The apparatus of claim 25, wherein the management instructions are operative to configure the data processing card:

to receive at the first data processing port a digital market data feed comprising a plurality of packets;

to identify packets that meet a first predetermined filtering criterion; and

to identify packets that meet a second predetermined filtering criterion;

wherein the first processed data consists of the packets that meet the first predetermined filtering criterion and the second processed data consists of the packets that meet the second predetermined filtering criterion.

27. The apparatus of claim 26, wherein the management instructions are operative to configure the digital crosspoint switch to replicate the first processed data from the second data processing port to a first plurality of the network interfaces.

28. The apparatus of claim 27, wherein the management instructions are operative to configure the digital crosspoint switch to replicate the second processed data from the third data processing port to a second plurality of the network interfaces.

29. The apparatus of claim 21, wherein the management instructions are further operative:

to provide a user interface for receiving user commands; and

to configure the data processing card and the digital crosspoint switch in accordance with the user commands.

30. The apparatus of claim 29, wherein the user interface is a command-line interface.