POWER UP OF SEMICONDUCTOR DEVICE HAVING A TEMPERATURE CIRCUIT AND METHOD THEREFOR

• US 20150276501A1
• Filed: 04/30/2014
• Published: 10/01/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Granted Patent: US 9,194,754 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence
• CPC Class Codes: G01K 7/16 using resistive elements resistive elements per se H01C, H01L
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Claims

1. A method of operating a device, comprising the steps of:

transitioning a power supply from a first potential to a second potential;

generating a first power up signal in response to the power supply potential transition;

initializing a counter circuit to provide a predetermined count value in response to the first power up signal; and

incrementally changing the count value in response to an output signal provided by a first temperature sensor circuit.

2. The method of operating the device of claim 1, wherein:

generating a second power up signal in response to the power supply potential transition.

3. The method of operating the device of claim 2, further including the steps of:

generating a load signal in response to the second power up signal; and

providing performance parameters from a performance parameter table based on the count value in response to the load signal.

4. The method of operating the device of claim 3, further including the step of:

latching the performance parameters to provide latched performance parameters.

5. The method of operating the device of claim 3, further including the step of:

adjusting operational aspects of performance parameter adjusted circuits in response to the values of the latched performance parameters.

6. The method of operating the device of claim 1, wherein:

the device is a semiconductor device.

7. A method of operating a device having a temperature circuit that provides a temperature window comprising the steps of:

initializing the temperature circuit to provide a first temperature window in response to transitioning a power supply from a first potential to a second potential wherein the device has a device temperature that is outside the first temperature window; and

adjusting the temperature circuit to provide a second temperature window that includes the device temperature.

8. The method of claim 7, wherein:

the step of adjusting includes incrementally changing a count value provided by a counter circuit.

9. The method of claim 8, further including the step of:

providing performance parameters from a performance parameter table based on the count value provided by the counter circuit after the step of adjusting the temperature circuit.

10. The method of claim 9, further including the step of:

generating a read signal after the step of adjusting the temperature circuit and the performance parameter table provides the performance parameters in response to the read signal.

11. The method of claim 10, further including the steps of:

generating a load signal after the step of generating the read signal; and

latching the performance parameters to provide latched performance parameters in response to the load signal.

12. A device, comprising:

power up circuit providing a first power up signal in response to a power supply transitioning from a first potential to a second potential;

a temperature circuit coupled to receive the first power up signal, the temperature circuit providing a first upper temperature limit value and a first lower temperature limit value in response to the first power up signal

wherein the device has a device temperature outside the first upper temperature limit value and the first lower temperature limit value.

13. The device of claim 12, further including:

a counter circuit coupled to receive the first power up signal, the counter circuit provides a count value having a predetermined value in response to the first power up signal wherein

the temperature circuit is coupled to receive the predetermined count value, the temperature circuit provides the first upper temperature limit value and the first lower temperature limit value in response to the predetermined count value.

14. The device of claim 13, further including:

the power up circuit provides a second power up signal; and

a performance parameter table coupled to provide performance parameters in response to the second power up signal.

15. The device of claim 14, further including:

a control circuit coupled to receive the second power up signal and provide a read signal wherein the performance parameter table provides the performance parameters in response to the read signal.

16. The device of claim 15, further including:

the control circuit provides a load signal; and

latch circuits coupled to receive the performance parameters and the load signal and provide latched performance parameters.

17. The device of claim 16, further including:

performance parameter adjusted circuits coupled to receive the latched performance parameters, performance parameter adjusted circuits have operational aspects adjusted in response to the values of the latched performance parameters.

18. The device of claim 17, further including:

the performance parameter table is a non-volatile memory.

19. The device of claim 12, wherein:

the temperature circuit is disabled in response to the first power up signal.

20. The device of claim 12, wherein:

the device is a semiconductor device.