SYSTEM ON CHIP METHOD THEREOF, AND DEVICE INCLUDING THE SAME

• US 20150277534A1
• Filed: 02/24/2015
• Published: 10/01/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sang Il Park
• Inventors: Park, Jong Lae, Lee, Woo Jin, Park, Sang IL, Lee, Gyeong Teak
• Granted Patent: US 9,632,567 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/163 Wearable computers, e.g. on a belt
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A Dynamic Voltage and Frequency Scaling (DVFS) method, comprising of a scheduling execution of DVFS to adjust frequency or voltage of a target device at a first scheduled time; monitoring operating frequency of the target device; and selectively deferring execution of DVFS at a later scheduled time based on the operating frequency of the target device; wherein execution of DVFS at a next scheduled time is deferred when the operating frequency of the target device is below a given minimum frequency.

Claims

1. A Dynamic Voltage and Frequency Scaling (DVFS) method, comprising:

scheduling execution of DVFS to adjust frequency or voltage of a target device at a first scheduled time;

monitoring operating frequency of the target device; and

selectively deferring execution of DVFS at a later scheduled time based on the operating frequency of the target device.

2. The method of claim 1, wherein execution of DVFS at a next scheduled time is deferred When the operating frequency of the target device is below a given minimum frequency.

3. The method of claim 1, wherein a CPU is selectively forced from idle to run state to execute DVFS based on the operating frequency of the target device.

4. The method of claim 3, wherein an idled CPU is not forced to run state to execute DVFS at a next scheduled time when the operating frequency of the target device is below a given minimum frequency.

5. The method of claim 1, wherein the target device is a memory interface.

6. The method of claim 1, wherein operating frequency or supplied voltage of the target device is reduced upon execution of DVFS.

7. A system on chip (SOC), comprising:

a CPU, a memory, and a target device controlled by the CPU, the memory having stored instructions executable by the CPU to;

schedule DVFS to adjust frequency or voltage of the target device at a first scheduled time;

monitor operating frequency of the target device; and

defer execution of DVFS at the next scheduled time when the operating frequency of the target device is below a given minimum frequency.

8. The SOC of claim 7, wherein the CPU is selectively forced from idle to run state to execute DVFS based on the operating frequency of the target device.

9. The SOC of claim 7, wherein the CPU is not forced from idle state to run state to execute DVFS at the next scheduled time when the operating frequency of the target device is below a given minimum frequency.

10. The SOC of claim 7, wherein the target device is a memory interface.

11. The SOC of claim 7, wherein the target device is a non-CPU IP.

12. The SOC of claim 7, further including a second target device controlled by the CPU, wherein the memory includes further stored instructions executable by the CPU to perform DVFS to adjust frequency or voltage of the second target device.

13. The Soc of claim 11, Wherein the second target device is an I/O interface.

14. The Soc of claim 7, wherein operating frequency or supplied voltage of the target device is reduced upon execution of DVFS.

15. The Soc of claim 7, embodied in one of a smartphone, a camera, a wearable smart device, or an internet of things (IoT).

16. A wearable electronic device, comprising:

a system on Chip (SOC), comprising;

a CPU, a memory, and a memory interface controlled by the CPU, the memory having stored instructions executable by the CPU to;

schedule DVFS to adjust frequency or voltage of a target device at a first scheduled time;

monitor operating frequency of the target device; and

selectively defer execution of DVFS at a later scheduled time based on the operating frequency of the target device;

a memory device connected to the memory interface; and

a display.

17. The wearable electronic device of claim 16, wherein the CPU is selectively forced from idle to run state to execute DVFS based on the operating frequency of the target device.

18. The wearable electronic device of claim 16, wherein the CPU is not forced from idle state to run state to execute DVFS at the next scheduled time when the operating frequency of the target device is below a given minimum frequency.

19. The wearable electronic device of claim 16, wherein the target device is a memory interface.

20. The wearable electronic device of claim 16, wherein the target device is a non-CPU IP.