METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCESSOR PIPELINE

• US 20150277916A1
• Filed: 03/28/2014
• Published: 10/01/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: NEELAKANTAM, NAVEEN, KHARTIKOV, DENIS M., KELM, JOHN H., XEKALAKIS, POLYCHRONIS
• Granted Patent: US 9,612,840 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/30152 Determining start or end of instruction; determining instruction length
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements

Abstract

A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

Claims

1. An apparatus comprising:

an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables;

a decode unit to decode the VLIWs in program order and output the syllables of each decoded VLIW in parallel; and

an out-of-order execution engine to execute at least some of the syllables in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

2. The apparatus as in claim 1 wherein the out-of-order execution engine includes register renaming logic to implement a read phase for reading logical register operands without use of a multiplexor and/or logical register operand comparators.

3. The apparatus as in claim 2 wherein the out-of-order execution engine further comprises scheduler setup logic to evaluate dependencies between syllables prior to scheduling of the syllables for execution by functional units, the schedule setup logic performed in parallel with the read phase of the register renaming logic.

4. The apparatus as in claim 3 wherein the scheduler setup logic is to further operate on each syllable in parallel with cancellation setup logic usable by the out-of-order execution engine to cancel effects of certain dispatched syllables.

5. The apparatus as in claim 1 further comprising:

a translator to translate program code from a high-level programming language or a public instruction set architecture (ISA) format to a private ISA format comprising the VLIWs and syllables.

6. The apparatus as in claim 5 wherein the translator comprises an optimizing compiler or binary translator, including, but not limited to, dynamic binary translator.

7. The apparatus as in claim 6 wherein the translator resolves data-flow dependencies and false output dependencies when translating to the private ISA format such that the syllables contained within each of VLIWs fetched in-order from memory do not have data-flow dependencies and false output dependencies.

8. The apparatus as in claim 7 wherein the data-flow dependencies comprise read-after-write (“

R-A-W”

) dependencies and the false output dependencies comprise write-after-write (“

W-A-W”

) dependencies.

9. The apparatus as in claim 8 wherein the translator allows false anti-data-flow dependencies within a VLIW.

10. The apparatus as in claim 9 wherein the false anti-data-flow dependencies comprise write-after-read (“

W-A-R”

) dependencies.

11. The apparatus as in claim 1 wherein the syllables are of multiple types including any combination of one or more control syllables, one or more floating-point vector syllables, one or more memory syllables, and/or one or more integer ALU syllables, where each syllable may be represented by a RISC instruction of a correspondent type.

12. The apparatus as in claim 11 wherein the syllable type is defined the allowed relative position of a syllable in a VLIW.

13. The apparatus as in claim 1 wherein the out-of-order execution engine includes dispatch logic to perform non-speculative early dispatch of syllables.

14. The apparatus as in claim 1 wherein the out-of-order execution engine is fully partitioned, including a register rename/allocation unit having N partitions and a scheduler unit having N partitions.

15. The apparatus as in claim 14 wherein the partitions are physically arranged to handle certain types of instructions.

16. The apparatus as in claim 15 wherein a first partition in the scheduler unit is associated with a first type of execution unit and a second partition in the scheduler unit is associated with a second type of execution unit.

17. The apparatus as in claim 14 wherein the partitioning of the rename/allocation unit and the scheduler unit reduces the number of write ports in the out-of-order execution engine and/or memory ordering buffer, including its load and store buffers.

18. The apparatus as in claim 5 wherein the public ISA comprise the Intel Architecture (IA).

24. The apparatus as in claim 7 wherein the data-flow dependencies comprise read-after-write (“

R-A-W”

) dependencies and the false output dependencies comprise write-after-write (“

W-A-W”

) dependencies.

19. An apparatus comprising:

a translator to translate program code from a public instruction set architecture (ISA) format to a private ISA format comprising Very Long Instruction Words (VLIWs), each of the VLIWs comprising a plurality of syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; and

an out-of-order execution engine to execute at least some of the syllables in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received by the out-of-order execution engine, the out-of-order execution engine comprising one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when handling the syllables.

20. The apparatus as in claim 19 wherein at least one of the stages comprise a register renaming stage which is to implement a read phase for reading physical register operands of syllables without use of a multiplexor or logical register operand comparators.

21. The apparatus as in claim 20 wherein the out-of-order execution engine further comprises scheduler setup logic to evaluate register data-flow dependencies between syllables prior to scheduling of the syllables for execution by execution units, the schedule setup logic performed in parallel with the read phase of the register renaming logic.

22. The apparatus as in claim 21 wherein the scheduler setup logic is to further operate on each syllable in parallel with cancellation setup logic usable by the out-of-order execution engine to cancel effects of certain dispatched syllables.

23. The apparatus as in claim 19 wherein the translator comprises an optimizing compiler or binary translator.

25. A method comprising:

translating program code from a public instruction set architecture (ISA) format to a private ISA format comprising Very Long Instruction Words (VLIWs), each of the VLIWs comprising a plurality of syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; and

executing at least some of the syllables by an out-of-order execution engine in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received by the out-of-order execution engine, the out-of-order execution engine comprising one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when handling the syllables.

26. The method as in claim 25 wherein the translator comprises an optimizing compiler or binary translator.

27. The method as in claim 26 wherein the data-flow dependencies comprise read-after-write (“

R-A-W”

) dependencies and the false output dependencies comprise write-after-write (“

W-A-W”

) dependencies.