CONTROL AREA FOR MANAGING MULTIPLE THREADS IN A COMPUTER

• US 20150277948A1
• Filed: 03/27/2014
• Published: 10/01/2015
• Est. Priority Date: 03/27/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Busaba, Fadi Y., Farrell, Mark S., Gainey, Charles W. Jr., Greiner, Dan F., Heller, Lisa Cranton, Kubala, Jeffrey P., Osisek, Damian L., Schmidt, Donald W., Slegel, Timothy J.
• Granted Patent: US 9,772,867 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Embodiments relate to a control area for managing multiple threads in a computer. An aspect is a computer system that includes a virtual machine (VM) configuration with one or more cores. Each core is enabled to operate in a single thread (ST) mode or a multithreading (MT) mode. The ST mode consists of a single thread and the MT mode consists of a plurality of threads on shared resources of a respective core. The computer system includes a core-oriented system control area (COSCA) having a common area representing all of the cores of the VM configuration and separate core description areas for each of the cores in the VM configuration. Each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread.

Claims

1. A computer system, comprising:

a virtual machine (VM) configuration comprising one or more cores, each core enabled to operate in a single thread (ST) mode or a multithreading (MT) mode, the ST mode consisting of single thread and the MT mode consisting of a plurality of threads on shared resources of a respective core;

a core-oriented system control area (COSCA) comprising a common area representing all of the one or more cores of the VM configuration and separate core description areas for each core of the one or more cores in the VM configuration, wherein each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread; and

a facility configured to control the configuration to perform a method comprising;

managing threads of the one or more cores of the VM configuration based on contents of the COSCA.

2. The computer system of claim 1, wherein the common area further indicates locations of the one or more separate core description areas for the one or more cores.

3. The computer system of claim 1, wherein the common area further includes a core validity mask that indicates a validity of the one or more cores.

4. The computer system of claim 1, wherein the core description area further includes a thread validity mask that indicates a validity of one or more threads associated with a core.

5. The computer system of claim 1, wherein each of the one or more state descriptions further indicates a location of the core description area of the respective core.

6. The computer system of claim 1, wherein each of the one or more state descriptions further indicates a location of the common area.

7. The computer system of claim 1, wherein at least one of:

each of the core description areas further indicates a location of the common area;

each of the state descriptions further indicates a location of a thread description area of the respective thread, each of the thread description areas further indicates a location of a core description area of the respective core, and each of the thread description areas further indicates the location of the common area.

8. The computer system of claim 1, wherein:

the common area further indicates locations of the one or more separate core description areas for the one or more cores;

the common area further includes a core validity mask that indicates a validity of the one or more cores; and

the core description area further includes a thread validity mask that indicates a validity of one or more threads associated with a core.

9. The computer system of claim 1, wherein the managing includes providing coordination between threads in the VM configuration.

10. The computer system of claim 1, wherein the managing includes modifying a content of a thread description area.

11. A computer-implemented method for managing multiple threads in a virtual machine (VM) configuration comprising one or more cores, each core enabled to operate in a single thread (ST) mode or a multithreading (MT) mode, the ST mode consisting of single thread and the MT mode consisting of a plurality of threads on shared resources of a respective core, the method comprising:

providing a core-oriented system control area (COSCA) comprising a common area representing all of the one or more cores of the VM configuration and separate core description areas for each core of the one or more cores in the VM configuration, wherein each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread; and

managing, by a core, threads of the one or more cores of the VM configuration based on contents of the COSCA.

12. The method of claim 11, wherein the common area further indicates locations of the one or more separate core description areas for the one or more cores.

13. The method of claim 11, wherein the common area further includes a core validity mask that indicates a validity of the one or more cores.

14. The method of claim 11, wherein the core description area further includes a thread validity mask that indicates a validity of one or more threads associated with a core.

15. The method of claim 11, wherein:

the common area further indicates locations of the one or more separate core description areas for the one or more cores;

the common area further includes a core validity mask that indicates a validity of the one or more cores; and

the core description area further includes a thread validity mask that indicates a validity of one or more threads associated with a core.

16. A computer program product for managing multiple threads in a virtual machine (VM) configuration comprising one or more cores, each core enabled to operate in a single thread (ST) mode or a multithreading (MT) mode, the ST mode consisting of single thread and the MT mode consisting of a plurality of threads on shared resources of a respective core, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a signal, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising;

providing a core-oriented system control area (COSCA) comprising a common area representing all of the one or more cores of the VM configuration and separate core description areas for each core of the one or more cores in the VM configuration, wherein each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread; and

managing, by a core, threads of the one or more cores of the VM configuration based on contents of the COSCA.

17. The computer program product of claim 16, wherein the common area further indicates locations of the one or more separate core description areas for the one or more cores.

18. The computer program product of claim 16, wherein the common area further includes a core validity mask that indicates a validity of the one or more cores.

19. The computer program product of claim 16, wherein the core description area further includes a thread validity mask that indicates a validity of one or more threads associated with a core.

20. The computer program product of claim 16, wherein:

the common area further indicates locations of the one or more separate core description areas for the one or more cores;

the common area further includes a core validity mask that indicates a validity of the one or more cores; and

the core description area further includes a thread validity mask that indicates a validity of one or more threads associated with a core.