Enabling Maximum Concurrency In A Hybrid Transactional Memory System
First Claim
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1. An apparatus comprising:
- a processor;
an execution logic to enable, in a transactional memory system, concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode;
a tracking logic to activate a flag to indicate that at least one software transaction is undergoing execution in the first software transaction mode or the second software transaction mode;
an intersection logic to determine whether, at a conclusion of a first hardware transaction of the second hardware transaction mode, a filter set of the first hardware transaction of the second hardware transaction mode conflicts with a filter set of the at least one software transaction undergoing execution; and
a finalization logic to commit the first hardware transaction if there is no conflict, and to abort the first hardware transaction if there is a conflict.
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Abstract
In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.
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Citations
25 Claims
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1. An apparatus comprising:
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a processor; an execution logic to enable, in a transactional memory system, concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode; a tracking logic to activate a flag to indicate that at least one software transaction is undergoing execution in the first software transaction mode or the second software transaction mode; an intersection logic to determine whether, at a conclusion of a first hardware transaction of the second hardware transaction mode, a filter set of the first hardware transaction of the second hardware transaction mode conflicts with a filter set of the at least one software transaction undergoing execution; and a finalization logic to commit the first hardware transaction if there is no conflict, and to abort the first hardware transaction if there is a conflict. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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concurrently executing, by a processor in a transactional memory system, a software transaction of a first thread and a hardware transaction of a second thread; activating a global lock to indicate execution of the software transaction; and at a conclusion of the hardware transaction, determining a state of the global lock and if the global lock is active, determining whether a filter set of the first thread intersects a filter set of the second thread, and if not, committing the hardware transaction. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. At least one computer-readable medium including instructions that when executed enable a system to:
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perform a second hardware transaction in a second hardware transaction mode of a transactional memory system; commit the second hardware transaction at a conclusion of the second hardware transaction; and after commitment of the second hardware transaction, invalidate at least one software transaction executing concurrently with the second hardware transaction if a conflict exists between the second hardware transaction and the at least one software transaction. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A system comprising:
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a processor including a hybrid transactional memory logic to perform at least one hardware transaction and at least one software transaction concurrently, wherein the hybrid transactional memory logic is to execute a first transaction in a first hardware transaction mode until the first transaction is committed or the first transaction is retried a first threshold number of times in the first hardware transaction mode, and thereafter if the first transaction is not committed, to execute the first transaction in a first software transaction mode, wherein the hybrid transactional memory logic includes an intersection logic to determine whether a filter set associated with the first transaction executed in the first hardware mode conflicts with a filter set associated with a second transaction executed in the first software transaction mode, and responsive to the conflict, the hybrid transactional memory logic is to prevent the first transaction in the first hardware transaction mode from commitment; and a transactional memory coupled to the processor. - View Dependent Claims (23, 24, 25)
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Specification