Enabling Maximum Concurrency In A Hybrid Transactional Memory System

• US 20150277967A1
• Filed: 03/26/2014
• Published: 10/01/2015
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Calciu, Irina, Gottschlich, Justin E., Shpeisman, Tatiana, Pokam, Gilles A.
• Granted Patent: US 9,971,627 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a processor;

an execution logic to enable, in a transactional memory system, concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode;

a tracking logic to activate a flag to indicate that at least one software transaction is undergoing execution in the first software transaction mode or the second software transaction mode;

an intersection logic to determine whether, at a conclusion of a first hardware transaction of the second hardware transaction mode, a filter set of the first hardware transaction of the second hardware transaction mode conflicts with a filter set of the at least one software transaction undergoing execution; and

a finalization logic to commit the first hardware transaction if there is no conflict, and to abort the first hardware transaction if there is a conflict.

2. The apparatus of claim 1, wherein in the second hardware transaction mode, the first hardware transaction is to update the filter set of the first hardware transaction for each memory access of the first hardware transaction.

3. The apparatus of claim 1, wherein in the first software transaction mode, a first software transaction is, at a conclusion of the first software transaction, to obtain a first lock and a second lock, and update a transactional memory of the transactional memory system with write data stored in a hash table.

4. The apparatus of claim 3, wherein in the first software transaction mode, after commitment of the first software transaction, the first software transaction is to invalidate another software transaction of the first software transaction mode.

5. The apparatus of claim 4, wherein in the second hardware transaction mode, a second hardware transaction is to obtain a commit lock and a transaction lock before commitment of the second hardware transaction.

6. The apparatus of claim 4, wherein the first software transaction is to invalidate the another software transaction if an intersection occurs between a filter set of the first software transaction and a filter set of the another software transaction.

7. The apparatus of claim 3, wherein in the first software transaction mode, the first software transaction is to validate read data during execution.

8. The apparatus of claim 1, wherein in the second software transaction mode:

at a beginning of a second software transaction, the second software transaction is to obtain a first lock and a second lock; and

during execution of the second software transaction in the second software transaction mode, the second software transaction is to directly update a transactional memory of the transactional memory system.

9. A method comprising:

concurrently executing, by a processor in a transactional memory system, a software transaction of a first thread and a hardware transaction of a second thread;

activating a global lock to indicate execution of the software transaction; and

at a conclusion of the hardware transaction, determining a state of the global lock and if the global lock is active, determining whether a filter set of the first thread intersects a filter set of the second thread, and if not, committing the hardware transaction.

10. The method of claim 9, further comprising committing the software transaction and deactivating the global lock at a conclusion of the software transaction.

11. The method of claim 9, further comprising committing the hardware transaction without determining whether the filter sets intersect when the global lock is inactive at the hardware transaction conclusion.

12. The method of claim 9, further comprising:

inserting an address of an access to a transactional memory of the transactional memory system by the hardware transaction into the filter set of the first thread; and

updating one or more fields of the filter set of the first thread based on hashing the address of the access with one or more hash values.

13. The method of claim 9, further comprising storing the filter set of the first thread in a write set of the first thread, the filter set comprising a Bloom filter.

14. The method of claim 13, further comprising adding the global lock to the filter set of the first thread and determining the state of the global lock based on determining whether the filter sets intersect.

15. The method of claim 9, further comprising:

concurrently re-hashing a hash table from a first size to a second size in the software transaction; and

accessing the hash table in the hardware transaction, and enabling the hardware transaction to commit during the concurrent re-hashing.

16. At least one computer-readable medium including instructions that when executed enable a system to:

perform a second hardware transaction in a second hardware transaction mode of a transactional memory system;

commit the second hardware transaction at a conclusion of the second hardware transaction; and

after commitment of the second hardware transaction, invalidate at least one software transaction executing concurrently with the second hardware transaction if a conflict exists between the second hardware transaction and the at least one software transaction.

17. The at least one computer-readable medium of claim 16, further comprising instructions that when executed enable the system, prior to commitment of the second hardware transaction, to determine if a commit lock has been acquired, and if so determine whether a conflict exists between the second hardware transaction and a first software transaction that has acquired the commit lock.

18. The at least one computer-readable medium of claim 17, further comprising instructions that when executed enable the system, if the conflict exists between the second hardware transaction and the first software transaction, to abort the second hardware transaction, wherein a conflict is determined to exist if a filter set of the second hardware transaction intersects a filter set of the first software transaction.

19. The at least one computer-readable medium of claim 17, further comprising instructions that when executed enable the system to:

perform a first hardware transaction in a first hardware transaction mode of the transactional memory system;

at a conclusion of the first hardware transaction, determine if at least one software transaction is concurrently executing; and

if so, abort the first hardware transaction, and otherwise commit the first hardware transaction.

20. The at least one computer-readable medium of claim 17, further comprising instructions that when executed enable the system to:

validate a read operation to a transactional memory of the transactional memory system by the first software transaction during execution of the first software transaction; and

if the read operation is validated, add a location of the read operation to a filter set of the first software transaction.

21. The at least one computer-readable medium of claim 17, further comprising instructions that when executed enable the system to:

perform a second software transaction in a second software transaction mode, including acquisition of a first lock and a commit lock at a beginning of execution of the second software transaction, and directly update one or more memory locations during the second software transaction execution; and

at a conclusion of the second software transaction, commit the second software transaction, invalidate one or more concurrently executing software transactions of the first software transaction mode, and thereafter release the first lock and the commit lock.

22. A system comprising:

a processor including a hybrid transactional memory logic to perform at least one hardware transaction and at least one software transaction concurrently, wherein the hybrid transactional memory logic is to execute a first transaction in a first hardware transaction mode until the first transaction is committed or the first transaction is retried a first threshold number of times in the first hardware transaction mode, and thereafter if the first transaction is not committed, to execute the first transaction in a first software transaction mode, wherein the hybrid transactional memory logic includes an intersection logic to determine whether a filter set associated with the first transaction executed in the first hardware mode conflicts with a filter set associated with a second transaction executed in the first software transaction mode, and responsive to the conflict, the hybrid transactional memory logic is to prevent the first transaction in the first hardware transaction mode from commitment; and

a transactional memory coupled to the processor.

23. The system of claim 22, wherein the hybrid transactional memory logic is to execute the first transaction in the first software transaction mode until the first transaction is committed or the first transaction is retried a second threshold number of times in the first software transaction mode, and after the second threshold number of times, to execute the first transaction in a second software transaction mode in which the first transaction is to directly update the transactional memory.

24. The system of claim 22, wherein the hybrid transactional memory logic is to execute the first transaction in a second hardware transaction mode prior to execution in the first hardware transaction mode, wherein the hybrid transactional memory logic is to execute the first transaction in the second hardware transaction mode for a third threshold number of times, prior to execution of the first transaction in the first hardware transaction mode.

25. The system of claim 22, wherein the hybrid transactional memory logic is to cause the first transaction to validate read data during execution in the first software transaction mode, update a filter set associated with the first transaction executed in the first software transaction mode based on an address associated with the read data, and update a hash table with write data.