ERROR CORRECTING (ECC) MEMORY COMPATIBILITY

• US 20150278012A1
• Filed: 03/28/2014
• Published: 10/01/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Gjorup, Karsten
• Granted Patent: US 9,495,232 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/141 for bus or memory accesses

Abstract

Host device platforms developed based on older ECC (Error Correcting Code) designs may not be equipped to handle the enhanced error correction capabilities in the newer NAND memories. Error correcting memory employing an error threshold representative of the additional capability of the ECC memory allows determining when a fetch has exceeded a safe level of errors to correct. ECC processing compares an error count to the threshold, and if the error count exceeds the threshold of maximum allowable errors, the ECC status module induces an error in the fetched data to alert the host.

Claims

1. A method of memory access, comprising:

comparing a corrected error count for a retrieved block of non-volatile memory to a threshold error value, the threshold error value set by a host in response to an Error Correcting Code (ECC) capability of the non-volatile memory; and

inducing an error in the retrieved block based on the threshold error value and transferring the retrieved block to the host.

2. The method of claim 1 further comprising generating an error count of a particular value if the corrected error count exceeds the threshold error value.

3. The method of claim 2 further comprising:

transferring the generated error count as part of the response to the read request.

4. The method of claim 2 wherein the threshold error value is indicative of a maximum number of errors per block that can be accommodated before generating the error count, the threshold error value specified by the host.

5. The method of claim 2 wherein the generated error count preempts a separate status exchange with the host for identifying a status of the retrieval.

6. The method of claim 1 further comprising transferring a successive retrieved block without transferring an error count status check with the host.

7. The method of claim 1 further comprising configuring the threshold error value based on the number of generated errors.

8. The method of claim 1 wherein the corrected error count is based on the number of bit errors in a contiguous portion of memory retrieved in the block.

9. The method of claim 2 further comprising:

identifying an error correction capability of the memory;

determining if the host is responsive to the error correction capability; and

receiving, from the host, an indication to set the threshold error value based on the identified error correction capability if the host does not correspond to the error correction capability of the memory, the host being responsive to the generated error count.

10. The method of claim 1 wherein the block is a page corresponding to a fetch instruction from the host.

11. A memory device comprising:

a memory operative to store and retrieve blocks;

a correction engine for identifying and correcting errors in the retrieved blocks;

a host interface responsive to a host for reading the stored blocks;

an error count, the error count generated by the correction engine;

a threshold error value, the threshold error value responsive to the host processor; and

an ECC status module for comparing the corrected error count to the threshold error value,

the host interface configured for transferring the retrieved block to the host, and further configured for inducing an error in the retrieved block if the corrected error count exceeds the threshold error value.

12. The memory device of claim 11 wherein the ECC status module is configured to modify the retrieved block to incorporate a 1-bit error.

13. The memory device of claim 12 wherein the host interface is configured to:

transfer the generated error count as part of the response to the read request.

14. The memory device of claim 12 wherein the threshold error value is preconfigured to be the maximum number of errors per block that the memory is capable of correcting.

15. The memory device of claim 12 wherein the generated error count preempts a separate status exchange with the host for identifying a status of the retrieval.

16. The memory device of claim 11 wherein the host interface is configured for transferring a successive retrieved block without transferring an error count status check with the host.

17. The memory device of claim 13, wherein the threshold error value comparison and data manipulation is done prior to transfer is done on each ECC block.

18. A computing device comprising:

a memory operative to store and retrieve blocks;

a correction engine for identifying and correcting errors in the retrieved blocks;

a host interface responsive to a host for exchanging the stored blocks;

an error count, the error count corrected by the correction engine;

a threshold error value, the threshold error value based on the ECC capability of the memory for identifying a number of errors correctable by the correction engine and for comparing the corrected error count to the threshold error value; and

an ECC status module for generating an error in the retrieved block if the corrected error count exceeds the threshold error value;

a display for rendering data in the retrieved blocks.

19. A computer program product having instructions encoded on a non-transitory computer readable storage medium that, when executed by a processor, perform a method of memory access, comprising:

comparing a corrected error count for a retrieved block of non-volatile memory to a threshold error value, the threshold error value set by a host in response to an Error Correcting Code (ECC) capability of the non-volatile memory, and;

transferring the retrieved block to the host error free if the corrected error count does not exceed the threshold error value; and

inducing an error in the retrieved block if the corrected error count exceeds the threshold error value.