CONTROL TRANSFER OVERRIDE

• US 20150278116A1
• Filed: 03/31/2014
• Published: 10/01/2015
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Paul Caprioli
• Inventors: CAPRIOLI, Paul
• Granted Patent: US 10,241,787 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/00 Arrangements for program control, e.g. control units program control for peripheral devices G06F13/10
• CPC Class Codes: G06F 9/322 for non-sequential address
• CPC Class Codes: G06F 9/328 for runtime instruction patching

Abstract

Embodiments of an invention for control transfer overrides are disclosed. In one embodiment, a processor includes an instruction unit to receive a control transfer instruction. The instruction unit includes a transfer override register to provide an alternative target for the control transfer instruction.

Claims

1. A processor comprising:

an instruction unit to receive a control transfer instruction, the instruction unit including a transfer override register to provide an alternative target for the control transfer instruction.

2. The processor of claim 1, wherein execution control of the processor is to be transferred to an original target of the control transfer instruction if the transfer override register is disabled.

3. The processor of claim 2, wherein execution control of the processor is to be transferred to the alternative target if the transfer override register is enabled.

4. The processor of claim 1, further comprising transfer override control logic to store a control transfer instruction source.

5. The processor of claim 2, further comprising transfer override control logic to store a control transfer instruction destination.

6. The processor of claim 5, wherein storing the control transfer instruction destination includes storing a pointer to the original target

7. The processor of claim 3, further a configuration register to be programmed to enable the transfer override register.

8. The processor of claim 7, wherein the configuration register includes one or more fields to provide information to selectively enable the transfer override register.

9. A method comprising:

programming, by software, a transfer override register in a processor to specify an alternative target of a control transfer instruction;

issuing, to the processor, a control transfer instruction having an original target;

transferring control of the processor to the alternative target instead of to the original target.

10. The method of claim 9, wherein programming the transfer override register includes storing, in the transfer override register, a pointer to the alternative target.

11. The method of claim 9, further comprising programming a configuration register to enable the transfer override register.

12. The method of claim 11, wherein control is transferred to the original target instead of to the alternative target is the transfer override register is disabled.

13. The method of claim 9, further comprising storing a control transfer instruction source.

14. The method of claim 9, further comprising storing a control transfer instruction destination.

15. The method of claim 14, wherein storing a control transfer instruction destination includes storing a pointer to the original target.

16. The method of claim 9, wherein the alternative target of the control transfer instruction is a location within a security layer.

17. The method of claim 16, further comprising examining, by the security layer, code associated with the original target.

18. The method of claim 17, further comprising determining, by the security layer, whether to transfer control to the original target, and transferring, in response to the determining, control to the original target.

19. A system comprising:

a memory in which to store first software and second software, wherein the first software includes a control transfer instruction having an original target in the second software; and

a processor including

an instruction unit to receive the control transfer instruction, the instruction unit including a transfer override register to provide an alternative target for the control transfer instruction.

20. The system of claim 19, wherein the memory is also in which to store a security layer, and the alternative target is within the security layer.