ELECTRONIC APPARATUS AND DISPLAY DRIVER
First Claim
1. An electronic apparatus comprisinga display panel;
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Accused Products
Abstract
In case that a terminal gradation signal output terminal in a pre-stage display driver and an initial gradation signal output terminal in a next-stage display driver of a plurality of display drivers which are arranged in parallel are used in driving the same gradation signal electrode of a display panel, an output of dummy data from the other gradation signal output terminal which mutually competes with an output timing of a gradation signal from one gradation signal output terminal between both the gradation signal output terminals is suppressed by high impedance control of a corresponding gradation signal output terminal.
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Citations
20 Claims
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1. An electronic apparatus comprising
a display panel; - and
a plurality of display-drivers which are disposed in series at an edge of the display panel in order to drive the display panel, wherein the display panel includes a plurality of sub-pixels in which selection terminals are connected to scanning signal electrodes and signal input terminals are connected to gradation signal electrodes, and wherein the plurality of sub-pixels form a plurality of scanning lines that extend in a direction of the scanning signal electrodes and a plurality of signal lines that extend in a direction of she gradation signal electrodes, and wherein the sub-pixels in a same signal line are alternately connected to adjacent gradation signal electrodes that are disposed on one of a first side of the same signal line and a second, opposite side of the same signal line, the display drivers are configured to supply gradation signals to a plurality of gradation signal electrodes in a parallel manner while driving the scanning signal electrodes in a predetermined order, wherein a first gradation signal output terminal disposed on a first display driver of the plurality of display drivers is adjacent to a second gradation signal output terminal disposed on a second display driver of the plurality of display drivers, wherein the first and second gradation signal output terminals are connected to a common gradation, signal electrode of the gradation signal electrodes, and wherein the first and second display drivers are adjacently located to each other at the edge of the display panel and. suppress an output of dummy data from the first and second gradation signal output terminals by using high impedance control associated with the first and second gradation signal output terminals to control an output of a gradation signal onto the common gradation signal electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A display driver comprising:
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a plurality of gradation signal output terminals, arranged in parallel, configured to output gradation signals in a parallel manner; a plurality of first output buffers configured to output a gradation signal of a first polarity to the gradation signal output terminals; a plurality of second output buffers configured to output a gradation signal of a second polarity to the gradation signal output terminals; an output switch circuit configured to switchably connect the first output buffers and second output buffers to corresponding gradation signal output terminals; and a timing control circuit configured to control an output of a gradation signal to a corresponding gradation signal output terminal from each of the first output buffers and the second output buffers in synchronization with display timing while alternately switching a switch state of the output switch circuit at a predetermined timing, wherein outputs of the first output buffers and the second output buffers that are selectively connected to gradation signal output terminals located on opposite ends of the display driver are configured to be selectively controlled in a high impedance state, and wherein the timing control circuit is configured to control the outputs in a high impedance state based on a dummy data output timing of one of the first output buffers and the second output buffers that are selectively connected to the gradation signal output terminals located on opposite ends of the display driver. - View Dependent Claims (13, 14, 15, 16)
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17. A display driver which is formed in one semiconductor substrate, the display driver comprising:
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a plurality of gradation signal output terminals, arranged in parallel, configured to output gradation signals in a parallel manner; a plurality of first output buffers configured to output a gradation signal of a first polarity to the gradation signal output terminals; a plurality of second output buffers configured to output a gradation signal of a second polarity to the gradation signal output terminals; an output switch circuit configured to switchably connect the first output buffers and second output buffers to corresponding gradation signal output terminals; and a timing control circuit configured to control an output of a gradation signal to a corresponding gradation signal output terminal from each of the first output buffers and the second output buffers in synchronization with display timing while alternately switching a switch state of the output switch circuit at a predetermined timing, wherein outputs of the first output buffers and the second output buffers that are selectively connected to gradation signal output terminals located on opposite ends of the display driver are configured to be selectively controlled in a high impedance state, and wherein the timing control circuit is configured to suppress an output of dummy data from at least one of the first output buffers and at least one of the second output buffers that are selectively connected to the gradation signal output terminals located on opposite ends of the display driver by using a high impedance control signal of the at least one of the first output buffers and the at least one of the second output buffers. - View Dependent Claims (18, 19, 20)
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Specification