DETERMINING A CELL STATE OF A RESISTIVE MEMORY CELL

• US 20150279458A1
• Filed: 03/23/2015
• Published: 10/01/2015
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Papandreou, Nikolaos, Pozidis, Charalampos, Sebastian, Abu, Stanisavljevic, Milos
• Granted Patent: US 9,343,148 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0057 Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage.

Claims

1. A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states, the device comprising:

a sensing circuit configured to sense a sensing voltage of the resistive memory cell and configured to output a resultant value in response to the sensing voltage which is indicative of the actual cell state;

a settling circuit configured to settle the sensing voltage to a certain target voltage representing one of the plurality M of programmable cell states;

a prebiasing circuit configured to prebiase a bitline capacitance of the resistive memory cell such that the sensing voltage is close to the certain target voltage; and

a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit.

2. The device of claim 1, wherein a resistance of the resistor is at least five times smaller than a highest resistance value of the resistive memory cell.

3. The device of claim 1, wherein a resistance of the resistor is between five and fifteen times smaller than a highest resistance value of the resistive memory cell.

4. The device of claim 1, wherein the prebiasing circuit is coupled to a first node connected to a bitline of the resistive memory cell and to the resistor.

5. The device of claim 4, further comprising:

a controller configured to control a number of switches such that, in a prebiasing phase, the prebiasing circuit is connected to the first node and, in a settling phase, the settling circuit is connected to the first node and the prebiasing circuit is disconnected from the first node.

6. The device of claim 5, further comprising:

a comparator configured to provide a comparison result based on comparing a first current flowing through the resistive memory cell and the resistor coupled in parallel to the resistive memory cell and a second current provided by a current mirror of the settling circuit.

7. The device of claim 6, wherein the controller is configured to control the number of switches such that the prebiasing circuit is connected to the first node as long as the comparison result indicates that the first current is smaller than the second current and such that the settling circuit is connected to the first node and the prebiasing circuit is disconnected from the first node if the comparison result indicates that the first current is greater than or equal to the second current.

8. The device of claim 7, wherein the controller is configured to feed, during the prebiasing phase, a number of gradual rising biasing voltages to the prebiasing circuit.

9. The device of claim 8, wherein the number of gradual rising biasing voltages includes a minimum biasing voltage corresponding to a maximum voltage allowed for the cell state having the lowest resistance value, a maximum biasing voltage corresponding to a maximum sensing voltage and gradual voltage steps between the minimum biasing voltage and the maximum biasing voltage.

10. The device of claim 6, wherein the comparator is a voltage comparator which is configured to provide the comparison result by comparing an output voltage provided by the current mirror of the settling circuit and a reference voltage.

11. The device of claim 4, wherein the prebiasing circuit includes a voltage regulator being coupleable by a first switch to a second node connected to the settling circuit and being coupleable by a second switch to the first node.

12. The device of claim 4, wherein the prebiasing circuit includes a serial connection of a voltage source, a resistor and a switch for connecting and disconnecting the prebiasing circuit to the first node.

13. The device of claim 12, wherein the resistor of the prebiasing circuit has an equal or lower resistance to the resistor coupled in parallel to the resistive memory cell.

14. A resistive memory device, comprising:

a memory including a plurality of resistive memory cells having a plurality of programmable levels; and

a read/write apparatus configured to read and write data in the plurality of resistive memory cells, wherein the read/write apparatus includes the device of claim 1.

15. (canceled)