TEMPERATURE COMPENSATION VIA MODULATION OF BIT LINE VOLTAGE DURING SENSING

• US 20150279472A1
• Filed: 03/26/2014
• Published: 10/01/2015
• Est. Priority Date: 03/26/2014
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jones, Mason
• Application Number:
  US14/226,354
• Publication Number:
  US 20150279472A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Embodiments of systems and methods described herein relate to temperature compensation of the sense conditions of memory cells during cross temperatures read operations. One embodiment provides a memory device comprising one or more memory cells, a temperature sensor and a controller coupled to the temperature sensor. The temperature sensor measures a temperature of at least one memory cell. The controller modulates a bit line voltage of the at least one memory cell during a program verify or read operation if the read temperature of the at least one memory cell is different from a first temperature of the memory cell.

Claims

1. A memory device, comprising:

one or more memory cells;

at least one temperature sensor to measure a temperature of at least one memory cell; and

a controller coupled to the at least one temperature sensor to modulate a bit line voltage of the at least one memory cell during a program verify or a read operation if a read temperature of the at least one memory cell is different from a first temperature of the memory cell.

2. The memory device according to claim 1, wherein the controller modulates the bit line voltage of the at least one memory cell during the program verify or the read operation by using an initial clamp voltage that is different from an initial clamp voltage that is used to program verify or read the at least one memory cell at the first temperature and by using a final clamp voltage that is different from a final clamp voltage that is used to program verify or read the at least one memory cell at the first temperature.

3. The memory device according to claim 2, wherein initial clamp voltage used during the program verify or read operation is about 200 mV different from the initial clamp voltage used to program verify or read the at least one memory cell at the first temperature and the final clamp voltage is about 200 mV different from the final clamp voltage used to program verify or read the at least one memory cell at the first temperature.

4. The memory device according to claim 1, wherein the one or more memory cells comprises one or more NAND-type string devices.

5. The memory device according to claim 1, wherein the one or more memory cells comprises one or more non-volatile memory cells.

6. The memory device according to claim 1, wherein the memory device comprises part of a solid-state drive (SSD).

7. The memory device according to claim 1, wherein the memory device comprises part of an array of memory devices.

8. A memory device, comprising:

one or more non-volatile memory cells arranged in rows and columns, each row of memory cells being coupled to a word line and each column of memory cells being coupled to a bit line;

at least one temperature sensor to measure a temperature of at least one memory cell; and

a controller coupled to the at least one temperature sensor to modulate a bit line voltage of the at least one memory cell during a program verify or a read operation if the read temperature of the at least one memory cell is different from a first temperature of the memory cell by a predetermined amount.

9. The memory device according to claim 8, wherein the controller modulates the bit line voltage of the at least one memory cell during the program verify or read operation by using an initial clamp voltage that is different from an initial clamp voltage that is used to program verity or read the at least one memory cell at the first temperature and by using a final clamp voltage that is different from a final clamp voltage that is used to program verify or read the at least one memory cell at the first temperature.

10. The memory device according to claim 9, wherein initial clamp voltage used during the program verify or read operation is about 200 mV different from the initial clamp voltage used to program verify or read the at least one memory cell at the first temperature and the final clamp voltage is about 200 mV different from the final clamp voltage is to program verify or read the at least one memory cell.

11. The memory device according to claim 8, wherein the one or more memory cells comprises one or more NAND-type string devices.

12. The memory device according to claim 8, wherein the memory device comprises part of a solid-state drive (SSD).

13. The memory device according to claim 8, wherein the memory device comprises part of an array of memory devices.

14. A method to temperature compensate a read operation of a memory device, the method comprising:

determining a temperature of the at least one memory cell if the at least one memory cell is to be program verified or read; and

modulating a bit line voltage coupled to the at least one memory cell if the program verify or read temperature of the at least one memory cell is different from a first temperature of the memory cell.

15. The method according to claim 14, wherein modulating the bit line comprises increasing an initial clamp voltage to the bit line to be different from an initial clamp voltage that is used to program verify or read the at least one memory cell at the first temperature and by increasing a final clamp voltage to the bit line to be different from than a final clamp voltage that is used to program verify or read the at least one memory cell at the first temperature.

16. The method according to claim 15, wherein initial clamp voltage used during the program verify or read operation is about 200 mV different from the initial clamp voltage used to program verify or read the at least one memory cell at the first temperature and the final clamp voltage is about 200 mV different from the final clamp voltage used to program verify or read the at least one memory cell at the first temperature.

17. The method according to claim 14, wherein the one or more memory cells comprises one or more NAND-type string devices.

18. The method according to claim 14, wherein the one or more memory cells comprises one or more non-volatile memory cells.

19. The method according to claim 14, wherein the memory device comprises part of a solid-state drive (SSD).

20. The method according to claim 14, wherein the memory device comprises part of an array of memory devices.