ANTI-FUSE ONE-TIME PROGRAMMABLE RESISTIVE RANDOM ACCESS MEMORIES

• US 20150279479A1
• Filed: 05/20/2014
• Published: 10/01/2015
• Est. Priority Date: 04/01/2014
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: LI, Xia, KANG, Seung Hyuk, LEE, Kangho, CHEN, Wei-Chuan
• Application Number:
  US14/283,154
• Publication Number:
  US 20150279479A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]

Abstract

An anti-fuse device includes a first electrode, an insulator on the first electrode, a second electrode on the insulator, and selector logic coupled to the second electrode. The device also includes a conductive path between the first and second electrodes. The conductive path may be configured to provide a hard breakdown for one-time programmable non-volatile data storage.

Claims

1. An anti-fuse device, comprising:

a first electrode;

an insulator on the first electrode;

a second electrode on the insulator;

selector logic coupled to the second electrode; and

a conductive path between the first and second electrodes configured to provide a hard breakdown for one-time programmable non-volatile data storage.

2. The anti-fuse device of claim 1, in which the insulator is composed of a dielectric material comprising hafnium oxide (HfO₂), titanium oxide (TiOx), thallium oxide (TlO₂), tungsten oxide (W₂O₃), and/or aluminum oxide (Al₂O₃).

3. The anti-fuse device of claim 1, in which the first electrode and the second electrode comprise titanium nitride (TiN), tantalum nitride (TaN), copper, aluminum and/or platinum.

4. The anti-fuse device of claim 1, in which the selector logic comprises a transistor having a gate, a first terminal and a second terminal.

5. The anti-fuse device of claim 1, in which the conductive path is formed by applying a high voltage and current value to the insulator.

6. The anti-fuse device of claim 1 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

7. A method of programming and reading a one-time programmable (OTP) device, comprising:

driving a current within at least a first cell of a resistive random access memory (RRAM) array to cause a hard breakdown of the first cell to provide one-time programming of data within the first cell; and

reading the data from the first cell.

8. The method of claim 7, further comprising:

un-programming a second cell of the RRAM array to enter a high resistance state for high resistance storage of another data within the second cell; and

differentially sensing data between the first cell and the second cell.

9. The method of claim 8, further comprising:

un-programming a third cell of the RRAM array to enter the high resistance state for high resistance storage of another data within the third cell;

differentially sensing cell state values from the first cell, the second cell, and the third cell; and

determining a final cell state value by analyzing the cell state values differentially sensed from the first cell, the second cell, and the third cell.

10. The method of claim 7, further comprising:

un-programming a second cell of the RRAM array to enter a low resistance state for low resistance storage of another data within the second cell; and

differentially sensing data between the first cell and the second cell.

11. The method of claim 10, further comprising:

un-programming a third cell of the RRAM array to enter the low resistance state for low resistance storage of another data within the third cell;

differentially sensing cell state values from the first cell, the second cell, and the third cell; and

determining a final cell state value by analyzing the cell state values differentially sensed from the first cell, the second cell, and the third cell.

12. The method of claim 7, further comprising:

driving the current within cells of the RRAM array to provide the hard breakdown of the cells for one-time programming storage of data within the cells; and

differentially sensing cell state values from the cells of the RRAM array to determine a final cell state value.

13. The method of claim 7, in which driving the current is performed using multiple pulses, a higher pulse or a pulse having a longer duration.

14. The method of claim 7, further comprising driving a reduced current within at least the first cell of the RRAM array to provide a soft breakdown of a second cell to provide multi-time programming of data within the second cell.

15. The method of claim 7, further comprising driving a reduced current within at least the first cell of the RRAM array to set a low resistance state or to reset a high resistance state of a second cell to provide multi-time programming of data within the second cell.

16. The method of claim 7, further comprising incorporating the OTP device into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

17. An anti-fuse device, comprising:

a first electrode;

an insulator on the first electrode;

a second electrode on the insulator;

selector logic coupled to the second electrode; and

means for conducting between the first and second electrodes to cause a hard breakdown for one-time programmable non-volatile storage.

18. The anti-fuse device of claim 17, in which the insulator is composed of a dialectic material comprising hafnium oxide (HfO₂), titanium oxide (TiOx), thallium oxide (TlO₂), tungsten oxide (W₂O₃), and/or aluminum oxide (Al₂O₃).

19. The anti-fuse device of claim 17, in which the first electrode and the second electrode comprise titanium nitride (TiN) and tantalum nitride (TaN), copper, aluminum and/or platinum.

20. The anti-fuse device of claim 17, in which the selector logic comprises a transistor having a gate, a first terminal and a second terminal.

21. The anti-fuse device of claim 17, in which the conducting means is formed by applying a high voltage and current value to the insulator.

22. The anti-fuse device of claim 17 incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

23. A method of programming and reading a OTP device, comprising the steps of:

driving a current within at least a first cell of a resistive random access memory (RRAM) array to cause a hard breakdown of the first cell to provide one-time programming of data within the first cell; and

reading the data from the first cell.

24. The method of claim 23, further comprising the step of incorporating the OTP device into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.