METHOD FOR FABRICATING SEMICONDUCTOR DEVICES HAVING HIGH-PRECISION GAPS

• US 20150279664A1
• Filed: 03/27/2015
• Published: 10/01/2015
• Est. Priority Date: 04/01/2014
• Status: Abandoned Application

• Current Assignee: Asia Pacific Microsystems Incorporated (Unimicron Technology Corporation)
• Original Assignee: Asia Pacific Microsystems Incorporated (Unimicron Technology Corporation)
• Inventors: Yin, Hung-Lin
• Application Number:
  US14/670,875
• Publication Number:
  US 20150279664A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B81C 1/00047 Cavities
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/461 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0355 Selective modification
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/05686 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80006 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80013 Plasma cleaning
• CPC Class Codes: H01L 2224/80894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/05442 : SiO2

Abstract

The present disclosure provides a method for fabricating semiconductor devices having high-precision gaps. The method includes steps of providing a first wafer; forming two or more regions having various ion dosage concentrations on a first surface of the first wafer; thermally oxidizing the first wafer so as to grow oxide layers with various thicknesses on the first surface of the first wafer; and bonding a second wafer to the thickest oxide layer of the first wafer so as to form one or more gaps.

Claims

1. A method for fabricating semiconductor devices, the method comprising the steps of:

providing a first wafer;

forming two or more regions on a first surface of the first wafer, the two or more regions including a first region characterized by a first oxidation rate and a second region characterized by a second oxidation rate, wherein the first region has a first ion dosage concentration, the second region has a second ion dosage concentration, and the first oxidation rate is higher than the second oxidation rate;

thermally oxidizing the first wafer so as to form a first oxide layer on the first region and a second oxide layer on the second region, wherein the first oxide layer is thicker than the second oxide layer; and

bonding a second wafer to the first oxide layer of the first wafer so as to form one or more gaps between the second wafer and the second oxide layer of the first wafer.

2. The method of claim 1, wherein the first ion dosage concentration is higher than the second ion dosage concentration.

3. The method of claim 1, wherein the first region contains a first type of ions and the second region contains a second type of ions.

4. The method of claim 3, wherein the first and second types of ions are selected from the group consisting of arsenic, phosphorus, antimony, and boron.

5. The method of claim 1, wherein the first and second wafers are selected from the group consisting of single crystal silicon wafer, polysilicon wafer, silicon carbide wafer, gallium arsenide wafer, and silicon-on-insulator wafer.

6. The method of claim 1, wherein

the first region includes a plurality of first sub-regions;

and

the second region includes a plurality of second sub-regions; and

wherein

the plurality of second sub-regions each are enclosed by a sub-region of the plurality of first sub-regions.

7. The method of claim 1, further comprising:

after bonding the second wafer to the first oxide layer of the first wafer, removing portions of the first or second wafers.

8. The method of claim 1, further comprising:

after bonding the second wafer to the first oxide layer of the first wafer,

etching the second wafer and the first oxide layer so as to expose portions of the first surface of the first wafer; and

forming one or more metal pads on the exposed portions of the first surface of the first wafer and one or more metal pads on a surface of the second wafer.

9. The method of claim 1, further comprising:

after bonding the second wafer to the first oxide layer of the first wafer,

etching the first wafer and the first oxide layer so as to expose portions of a surface of the second wafer; and

forming one or more metal pads on the exposed portions of the surface of the second wafer and one or more metal pads on the first surface of the first wafer.

10. The method of claim 1, further comprising:

after bonding the second wafer to the first oxide layer of the first wafer, singulating semiconductor devices from the bonded first and second wafers.

11. The method of claim 1, further comprising:

after bonding the second wafer to the first oxide layer of the first wafer, removing portions of the first or second wafers;

etching the second wafer and the first oxide layer so as to expose portions of the first surface of the first wafer;

forming one or more metal pads on the exposed portions of the first surface of the first wafer and one or more metal pads on a surface of the second wafer; and

singulating semiconductor devices from the bonded first and second wafers.

12. The method of claim 1, further comprising:

after bonding the second wafer to the first oxide layer of the first wafer, removing portions of the first or second wafers;

etching the first wafer and the first oxide layer so as to expose portions of a surface of the second wafer;

forming one or more metal pads on the exposed portions of the surface of the second wafer and one or more metal pads on the first surface of the first wafer; and

singulating semiconductor devices from the bonded first and second wafers.

13. The method of claim 1, wherein

the two or more regions further include a third region characterized by a third oxidation rate;

the third oxidation rate is lower than the first oxidation rate and is higher than the second oxidation rate;

a third oxide layer is formed on the third region in the step of thermally oxidizing the first wafer; and

the third oxide layer is thinner than the first oxide layer and is thicker than the second oxide layer.

14. The method of claim 13, wherein

the first region includes a plurality of first sub-regions;

the second region includes a plurality of second sub-regions; and

the third region includes a plurality of third sub-regions; and

wherein

the plurality of second sub-regions each are enclosed by a sub-region of the plurality of third sub-regions; and

the plurality of third sub-regions each are enclosed by a sub-region of the plurality of first sub-regions.

15. The method of claim 1, further comprising:

after thermally oxidizing the first wafer and prior to bonding the second wafer to the first oxide layer of the first wafer, thermally oxidizing the second wafer so as to form an oxide layer on a surface of the second wafer, wherein bonding the second wafer to the first oxide layer of the first wafer is to bond the oxide layer on the surface of the second wafer to the first oxide layer of the first wafer.

16. The method of claim 1, further comprising:

after thermally oxidizing the first wafer and prior to bonding the second wafer to the first oxide layer of the first wafer,

forming two or more regions on a first surface of the second wafer, the two or more regions on the first surface of the second wafer including a third region characterized by a third oxidation rate and a fourth region characterized by a fourth oxidation rate, wherein the third oxidation rate is higher than the fourth oxidation rate; and

thermally oxidizing the second wafer so as to form a third oxide layer on the third region and a fourth oxide layer on the fourth region, wherein the third oxide layer is thicker than the fourth oxide layer, wherein bonding the second wafer to the first oxide layer of the first wafer is to bond the third oxide layer of the second wafer to the first oxide layer of the first wafer.