Bonding Structure for Stacked Semiconductor Devices

• US 20150279816A1
• Filed: 03/28/2014
• Published: 10/01/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Szu-Ying, Yaung, Dun-Nian
• Granted Patent: US 9,230,941 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/03616 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/0382 Applying permanent coating, e.g. in-situ coating
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06517 including bonding areas providing primarily mechanical bonding
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/09515 Bonding areas having different functions
• CPC Class Codes: H01L 2224/09517 including bonding areas providing primarily mechanical support
• CPC Class Codes: H01L 2224/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80011 Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/80012 Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
• CPC Class Codes: H01L 2224/80013 : Plasma cleaning
• CPC Class Codes: H01L 2224/80014 : Thermal cleaning, e.g. decomposition, sublimation
• CPC Class Codes: H01L 2224/8034 : Bonding interfaces of the bonding area
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/8036 : Bonding interfaces of the semiconductor or solid state body
• CPC Class Codes: H01L 2224/80894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H01L 27/14685 : Process for coatings or optical elements
• CPC Class Codes: H01L 27/1469 : Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns

Abstract

A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first bonding pad, a second bonding pad, and a first via are formed in the recesses. In some embodiment, the first via may have electrical contact with the first bonding pad and may provide an electrical pathway to a first plurality of metallization layers. The first bonding pad and the second bonding pad in the first substrate are aligned to a third bonding pad and the fourth bonding pad in a second substrate and may be bonded using a direct bonding method. A bond between the first bonding pad and the third bonding pad may provide an electrical pathway between devices on the first substrate and devices on the second substrate.

Claims

1. A semiconductor device comprising:

a first structure comprising;

a first substrate having a first side, the first substrate comprising a first semiconductor substrate;

a first metallization layer on the first side of the first substrate;

a first passivation layer on the first metallization layer;

a first conductive pad in the first metallization layer; and

a first bonding pad and a first via in the first passivation layer, the first via being interposed between the first bonding pad and the first conductive pad, the first bonding pad and the first via being in direct electrical contact, and the first via and the first conductive pad being in direct electrical contact;

a second structure directly bonded to the first structure, the second structure comprising;

a second substrate having a second side, the second side facing the first side, the second substrate comprising a second semiconductor substrate;

a second metallization layer on the second side of the second substrate;

a second passivation layer on the second metallization layer;

a second conductive pad in the second metallization layer; and

a second bonding pad in the second passivation layer, the second bonding pad being in direct electrical contact with the second conductive pad; and

wherein the second structure is bonded to the first structure such that the first bonding pad and the second bonding pad are aligned with respect to each other.

2. The semiconductor device of claim 1, further comprising a third bonding pad in the first passivation layer, the third bonding pad being electrically isolated from the first metallization layer.

3. The semiconductor device of claim 1, further comprising a fourth bonding pad in the second passivation layer, the fourth bonding pad being electrically isolated from the second metallization layer.

4. The semiconductor device of claim 1, wherein the first bonding pad has a height between about 100 nm and about 900 nm, and a width between about 0.6 μ

m and about 3 μ

m.

5. The semiconductor device of claim 1, wherein the first via has a height between about 100 nm and about 400 nm, and a width between about 0.1 μ

m and about 0.4 μ

m.

6. The semiconductor device of claim 1, wherein the first conductive pad has a height between about 90 nm and about 900 nm, and a width between about 0.09 μ

m and about 0.4 μ

m.

7. The semiconductor device of claim 1, wherein the first structure is bonded to the second structure using a hybrid bonding method.

8. A semiconductor device comprising:

a first structure comprising;

a first substrate having a first side, the first substrate comprising a semiconductor substrate;

a first plurality of metallization layers on the first side of the first substrate;

a first passivation layer on the first plurality of metallization layers;

a first plurality of conductive pads in a topmost metallization layer of the first plurality of metallization layers; and

a first plurality of bonding pads and a first plurality of vias in the first passivation layer, wherein each of the vias provides direct electrical contact between respective ones of the first plurality of bonding pads and the first plurality of conductive pads;

a second structure directly bonded to the first structure, the second structure comprising;

a second substrate having a second side, the second side facing the first side;

at least one active device on the second side of the second substrate;

a second plurality of metallization layers on the second side of the second substrate;

a second passivation layer on the second plurality of metallization layers;

a second plurality of conductive pads in a topmost metallization layer of the second plurality of metallization layers; and

a second plurality of bonding pads in the second passivation layer, each of the second plurality of bonding pads being in direct electrical contact with a respective one of the second plurality of conductive pads; and

wherein the second structure is bonded to the first structure such that the first plurality of bonding pads and the second plurality of bonding pads are aligned with respect to each other.

9. The semiconductor device of claim 8, further comprising one or more first dummy bonding pads in the first passivation layer.

10. The semiconductor device of claim 9, further comprising one or more second dummy bonding pads in the second passivation layer.

11. The semiconductor device of claim 8, wherein the first plurality of bonding pads have a height between about 100 nm and about 900 nm, and a width between about 0.6 μ

m and about 3 μ

m.

12. The semiconductor device of claim 8, wherein the first plurality of vias have a height between about 100 nm and about 400 nm, and a width between about 0.1 μ

m and about 0.4 μ

m.

13. The semiconductor device of claim 8, wherein the first plurality of conductive pads have a height between about 90 nm and about 900 nm, and a width between about 0.09 μ

m and about 0.4 μ

m.

14. The semiconductor device of claim 8, wherein the first structure is bonded to the second structure using a hybrid bonding method.

15. A method of fabrication of a semiconductor device, the method comprising:

forming a first metallization layer over a first substrate;

forming a first conductive pad in the first metallization layer;

forming a first passivation layer over the first metallization layer;

forming a first bonding pad and a first via in the first passivation layer, the first via being in direct physical contact with the first bonding pad and the first conductive pad;

forming a second metallization layer over a second substrate;

forming a second conductive pad in the second metallization layer;

forming a second passivation layer over the second metallization layer;

forming a second bonding pad in the second passivation layer, the second bonding pad being in direct physical contact with the second conductive pad; and

after forming the first bonding pad, the first via and the second bonding pad, bonding the first substrate to the second substrate.

16. The method of claim 15, further comprising forming a first dummy bonding pad in the first passivation layer.

17. The method of claim 16, further comprising forming a second dummy bonding pad in the second passivation layer.

18. The method of claim 15, wherein the first bonding pad has a height between about 100 nm and about 900 nm, and a width between about 0.6 μ

m and about 3 μ

m.

19. The method of claim 15, wherein the first via has a height between about 100 nm and about 400 nm, and a width between about 0.1 μ

m and about 0.4 μ

m.

20. The method of claim 15, wherein the first conductive pad has a height between about 90 nm and about 900 nm, and a width between about 0.09 μ

m and about 0.4 μ

m.