Power Semiconductor Device with Embedded Field Electrodes
First Claim
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1. A power semiconductor device comprising:
- an upper drift region situated over a lower drift region;
a plurality of field electrode embedded in said lower drift region;
at least one of said plurality of field electrode not being directly aligned with a gate trench in a body region of said power semiconductor device;
wherein respective top surfaces of said at least one of said plurality of field electrode and said lower drift region are substantially co-planar.
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Abstract
A power semiconductor device is disclosed. The power semiconductor device includes an upper drift region situated over a lower drift region, a field electrode embedded in the lower drift region, the field electrode not being directly aligned with a gate trench in a body region of the power semiconductor device, where respective top surfaces of the field electrode and the lower drift region are substantially co-planar. A conductive filler in the field electrode can be substantially uniformly doped, and the field electrode is in direct electrical contact with the upper drift region.
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Citations
20 Claims
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1. A power semiconductor device comprising:
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an upper drift region situated over a lower drift region; a plurality of field electrode embedded in said lower drift region; at least one of said plurality of field electrode not being directly aligned with a gate trench in a body region of said power semiconductor device; wherein respective top surfaces of said at least one of said plurality of field electrode and said lower drift region are substantially co-planar. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A power semiconductor device comprising:
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an upper drift region situated over a lower drift region; a field electrode embedded in said lower drift region; said field electrode not being directly aligned with a gate trench in a body region of said power semiconductor device; wherein respective top surfaces of said field electrode and said lower drift region are substantially co-planar; wherein a conductive filler in said field electrode is substantially uniformly doped. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method comprising:
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forming a lower drift region over a semiconductor substrate; forming a trench in said lower drift region; forming an insulation material lining said trench; depositing a conductive filler in said trench to form a field electrode; planarizing said field electrode with said lower drift region; forming an upper drift region over said lower drift region; forming a gate trench for a power semiconductor device, wherein said gate trench is not directly aligned with said field electrode. - View Dependent Claims (18, 19, 20)
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Specification