Power Semiconductor Device with Embedded Field Electrodes

• US 20150279946A1
• Filed: 02/27/2015
• Published: 10/01/2015
• Est. Priority Date: 03/26/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Henson, Timothy D.
• Granted Patent: US 9,761,676 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device is disclosed. The power semiconductor device includes an upper drift region situated over a lower drift region, a field electrode embedded in the lower drift region, the field electrode not being directly aligned with a gate trench in a body region of the power semiconductor device, where respective top surfaces of the field electrode and the lower drift region are substantially co-planar. A conductive filler in the field electrode can be substantially uniformly doped, and the field electrode is in direct electrical contact with the upper drift region.

Claims

1. A power semiconductor device comprising:

an upper drift region situated over a lower drift region;

a plurality of field electrode embedded in said lower drift region;

at least one of said plurality of field electrode not being directly aligned with a gate trench in a body region of said power semiconductor device;

wherein respective top surfaces of said at least one of said plurality of field electrode and said lower drift region are substantially co-planar.

2. The power semiconductor device of claim 1, wherein each of said plurality of field electrodes comprises a conductive filler and an insulation material in a trench in said lower drift region.

3. The power semiconductor device of claim 1, wherein said plurality of field electrodes comprise polysilicon.

4. The power semiconductor device of claim 1, wherein said plurality of field electrodes comprise amorphous silicon.

5. The power semiconductor device of claim 1, wherein said plurality of field electrodes are held at approximately an intermediate potential between a source and a drain of said power semiconductor device under reverse bias.

6. The power semiconductor device of claim 1, wherein respective top surfaces of said plurality of field electrodes are substantially co-planar.

7. The power semiconductor device of claim 1, wherein said at lease one of said plurality of field electrode is situated below a source of said power semiconductor device.

8. The power semiconductor device of claim 1, wherein said plurality of field electrodes are in direct electrical contact with said upper drift region.

9. A power semiconductor device comprising:

an upper drift region situated over a lower drift region;

a field electrode embedded in said lower drift region;

said field electrode not being directly aligned with a gate trench in a body region of said power semiconductor device;

wherein respective top surfaces of said field electrode and said lower drift region are substantially co-planar;

wherein a conductive filler in said field electrode is substantially uniformly doped.

10. The power semiconductor device of claim 9, wherein said field electrode comprises a conductive filler and an insulation material in a trench in said lower drift region.

11. The power semiconductor device of claim 9, wherein said field electrode comprises polysilicon.

12. The power semiconductor device of claim 9, wherein said field electrode comprises amorphous silicon.

13. The power semiconductor device of claim 9, wherein said field electrode is held at approximately an intermediate potential between a source and a drain of said power semiconductor device under reverse bias.

14. The power semiconductor device of claim 9, further comprising another field electrode in said lower drift region, wherein said top surface of said field electrode is substantially co-planar with a top surface of said another field electrode.

15. The power semiconductor device of claim 9, wherein said field electrode is situated below a source of said power semiconductor device.

16. The power semiconductor device of claim 9, wherein said field electrode is in direct electrical contact with said upper drift region.

17. A method comprising:

forming a lower drift region over a semiconductor substrate;

forming a trench in said lower drift region;

forming an insulation material lining said trench;

depositing a conductive filler in said trench to form a field electrode;

planarizing said field electrode with said lower drift region;

forming an upper drift region over said lower drift region;

forming a gate trench for a power semiconductor device, wherein said gate trench is not directly aligned with said field electrode.

18. The method of claim 17, wherein said planarizing comprises chemical mechanical polishing.

19. The method of claim 17, wherein said field electrode is situated under a source of said power semiconductor device.

20. The method of claim 17, wherein said conductive filler of said field electrode has a substantially uniform doping concentration and is in direct electrical contact with said upper drift region.