RAPID TRANSITION SCHMITT TRIGGER CIRCUIT

• US 20150280694A1
• Filed: 06/15/2015
• Published: 10/01/2015
• Est. Priority Date: 12/17/2012
• Status: Active Grant

• Current Assignee: Smarter Microelectronics (Guangzhou) Co.,Ltd
• Original Assignee: Smarter Microelectronics (Guangzhou) Co.,Ltd
• Inventors: LI, YANG
• Granted Patent: US 9,584,101 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process includes: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit; wherein, the PMOS/NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

Claims

1. A small-sized rapid transition Schmitt trigger circuit for use with a silicon-on-insulator process, comprising:

a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit;

wherein, the PMOS/NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

2. The circuit of claim 1, wherein the PMOS/NMOS body control circuit is configured to, through controlling voltages of body regions of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

3. The circuit of claim 1, wherein a gate electrode of the first PMOS transistor is connected to an input end, a source electrode of the first PMOS transistor is connected to a power supply, a drain electrode of the first PMOS transistor is connected to an inter-stage common node;

a gate electrode of the second PMOS transistor is connected to an inter-stage common node, the source electrode of the second transistor is connected to the power supply, the drain electrode of the second PMOS transistor is connected to the output end.

4. The circuit of claim 3, wherein the gate electrode of the first NMOS transistor is connected to the input end, the source electrode of the first NMOS transistor is connected to the ground, the drain electrode of the first transistor is connected to the inter-stage common node;

the gate electrode of the second NMOS transistor is connected to the inter-stage common node, the source electrode of the second NMOS transistor is connected to the ground, the drain electrode of the second NMOS transistor is connected to the output end.

5. The circuit of claim 2, wherein the PMOS/NMOS body control circuit is configured as:

if the input of the Schmitt trigger is at a low electrical level, set the voltage of the body region of the first NMOS transistor to 0, and set the voltage of the body region of the first PMOS transistor to V_D1;

if the input of the Schmitt trigger is high electrical level, set the voltage of the body region of the first NMOS transistor to V_D2, and set the voltage of the body region of the first PMOS transistor to V_DD;

wherein, V_DD represents the power supply voltage, V_D1 represents the low voltage outputted by the first output end of PMOS/NMOS body control circuit, said first output end is connected to the body region of the first PMOS transistor;

V_D2 represents the high voltage outputted by the second output end of the PMOS/NMOS transistor body control circuit, said second output end is connected to the body region of the first NMOS transistor.

6. The circuit of claim 5, wherein said PMOS/NMOS body control circuit comprises:

a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first diode, a resistor and a second diode.

7. The circuit of claim 6, wherein, the drain electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected to the body region of the first PMOS transistor;

the drain electrode of the fourth NMOS and the source electrode of the third NMOS transistor are connected to the body region of the first NMOS transistor;

the gate electrode of the third NMOS transistor is connected to the gate electrode and the gate electrode of the fourth PMOS transistor and the output end;

the gate electrode of the fourth NMOS transistor is connected to the gate electrode of the third PMOS transistor;

the source electrode of the fourth NMOS transistor is connected to the ground, the source electrode of the third PMOS transistor is connected to the power supply;

the cathode of the first diode is connected to the power supply, the anode of the first diode is connected to one end of the resistor and the drain electrode of the fourth PMOS transistor;

the anode of the second diode is connected to the ground, the cathode of the second diode is connected to the other end of the resistor and the drain electrode of the third NMOS transistor.

8. An silicon-on-insulator-based integrated circuit comprising a rapid transition Schmitt trigger circuit, the Schmitt trigger circuit including:

a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit;

wherein, the PMOS/NMOS body control circuit is configured to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

9. The integrated circuit of claim 8, wherein the PMOS/NMOS body control circuit is configured to, through controlling voltages of body regions of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

10. The integrated circuit of claim 8, wherein a gate electrode of the first PMOS transistor is connected to an input end, a source electrode of the first PMOS transistor is connected to a power supply, a drain electrode of the first PMOS transistor is connected to an inter-stage common node;

a gate electrode of the second PMOS transistor is connected to an inter-stage common node, the source electrode of the second transistor is connected to the power supply, the drain electrode of the second PMOS transistor is connected to the output end.

11. The integrated circuit of claim 10, wherein, the gate electrode of the first NMOS transistor is connected to the input end, the source electrode of the first NMOS transistor is connected to the ground, the drain electrode of the first transistor is connected to the inter-stage common node;

the gate electrode of the second NMOS transistor is connected to the inter-stage common node, the source electrode of the second NMOS transistor is connected to the ground, the drain electrode of the second NMOS transistor is connected to the output end.

12. The integrated circuit of claim 9, wherein the PMOS/NMOS body control circuit is configured as:

when the input of the Schmitt trigger is low electrical level, se the voltage of the body region of the first NMOS transistor to 0, and set the voltage of the body region of the first PMOS transistor to V_D1;

when the input of the Schmitt trigger is high electrical level, set the voltage of the body region of the first NMOS transistor to V_D2, and set the voltage of the body region of the first PMOS transistor to V_DD;

wherein, V_DD represents the power supply voltage, V_D1 represents the low voltage outputted by the first output end of PMOS/NMOS body control circuit, said first output end is connected to the body region of the first PMOS transistor;

V_D2 represents the high voltage outputted by the second output end of the PMOS/NMOS transistor body control circuit, said second output end is connected to the body region of the first NMOS transistor.

13. The integrated circuit of claim 12, wherein said PMOS/NMOS body control circuit comprises:

a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first diode, a resistor and a second diode.

14. The integrated circuit of claim 13, wherein the drain electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected to the body region of the first PMOS transistor;

the drain electrode of the fourth NMOS and the source electrode of the third NMOS transistor are connected to the body region of the first NMOS transistor;

the gate electrode of the third NMOS transistor is connected to the gate electrode and the gate electrode of the fourth PMOS transistor and the output end;

the gate electrode of the fourth NMOS transistor is connected to the gate electrode of the third PMOS transistor;

the source electrode of the fourth NMOS transistor is connected to the ground, the source electrode of the third PMOS transistor is connected to the power supply;

the cathode of the first diode is connected to the power supply, the anode of the first diode is connected to one end of the resistor and the drain electrode of the fourth PMOS transistor;

the anode of the second diode is connected to the ground, the cathode of the second diode is connected to the other end of the resistor and the drain electrode of the third NMOS transistor.

15. A method of realizing, in a silicon-on-insulator-based integrated circuit, a rapid transition with a Schmitt trigger circuit, wherein the Schmitt trigger circuit includes:

a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, and a PMOS/NMOS body control circuit;

the method comprising;

configuring the PMOS/NMOS body control circuit to, through changing threshold voltages of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

16. The method of claim 15, wherein the PMOS/NMOS body control circuit is configured to, through controlling voltages of body regions of the first NMOS transistor and the first PMOS transistor, enable different flip-flop threshold voltages for input transitions from high electrical levels to low electrical levels and from low electrical levels to high electrical levels.

17. The method of claim 15, wherein a gate electrode of the first PMOS transistor is connected to an input end, a source electrode of the first PMOS transistor is connected to a power supply, a drain electrode of the first PMOS transistor is connected to an inter-stage common node;

a gate electrode of the second PMOS transistor is connected to an inter-stage common node, the source electrode of the second transistor is connected to the power supply, the drain electrode of the second PMOS transistor is connected to the output end.

18. The method of claim 17, wherein the gate electrode of the first NMOS transistor is connected to the input end, the source electrode of the first NMOS transistor is connected to the ground, the drain electrode of the first transistor is connected to the inter-stage common node;

the gate electrode of the second NMOS transistor is connected to the inter-stage common node, the source electrode of the second NMOS transistor is connected to the ground, the drain electrode of the second NMOS transistor is connected to the output end.

19. The method of claim 16, wherein the PMOS/NMOS body control circuit is configured as:

when the input of the Schmitt trigger is low electrical level, se the voltage of the body region of the first NMOS transistor to 0, and set the voltage of the body region of the first PMOS transistor to V_D1;

when the input of the Schmitt trigger is high electrical level, set the voltage of the body region of the first NMOS transistor to V_D2, and set the voltage of the body region of the first PMOS transistor to V_DD;

wherein, V_DD represents the power supply voltage, V_D1 represents the low voltage outputted by the first output end of PMOS/NMOS body control circuit, said first output end is connected to the body region of the first PMOS transistor;

V_D2 represents the high voltage outputted by the second output end of the PMOS/NMOS transistor body control circuit, said second output end is connected to the body region of the first NMOS transistor.

20. The method of claim 19, wherein said PMOS/NMOS body control circuit comprises:

a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first diode, a resistor and a second diode; and

wherein the drain electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected to the body region of the first PMOS transistor;

the drain electrode of the fourth NMOS and the source electrode of the third NMOS transistor are connected to the body region of the first NMOS transistor;

the gate electrode of the third NMOS transistor is connected to the gate electrode and the gate electrode of the fourth PMOS transistor and the output end;

the gate electrode of the fourth NMOS transistor is connected to the gate electrode of the third PMOS transistor;

the source electrode of the fourth NMOS transistor is connected to the ground, the source electrode of the third PMOS transistor is connected to the power supply;

the cathode of the first diode is connected to the power supply, the anode of the first diode is connected to one end of the resistor and the drain electrode of the fourth PMOS transistor;

the anode of the second diode is connected to the ground, the cathode of the second diode is connected to the other end of the resistor and the drain electrode of the third NMOS transistor.