VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR WIDE SUPPLY VOLTAGE APPLICATIONS

• US 20150280714A1
• Filed: 03/31/2014
• Published: 10/01/2015
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: KUMAR, Vinod
• Granted Patent: US 9,748,957 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 19/0185 using field effect transistors only
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration
• CPC Class Codes: H03K 3/356165 using additional transistors in the feedback circuit

Abstract

A level shifter circuit is configured to receive first and second complementary input signals. Each of the first and second complementary input signals have a value of either a first supply voltage or a first reference voltage. The level shifter further includes a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and includes a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage.

Claims

1. A level shifter circuit configured to receive first and second complementary input signals, each of the first and second complementary input signals having a value of either a first supply voltage or a first reference voltage and the level shifter further including a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second complementary output signals to a second supply voltage and including a weak latch circuit operable to drive the other of the first and second complementary output signals to a second reference voltage.

2. The level shifter circuit of claim 1,

wherein the strong latch circuit is coupled between a first supply voltage node and first and second complementary output nodes on which the first and second output signals are provided, respectively;

and

wherein the weak latch circuit is coupled between a first reference voltage node and the first and second complementary output nodes.

3. The level shifter circuit of claim 2, further comprising:

a first input signal write circuit coupled between the first complementary output node and a second supply voltage node, the first input signal write circuit configured to receive the first complementary input signal on a first complementary input node and operable in response to the first complementary input signal to cause the strong latch circuit to drive the second output signal on the second complementary output node to approximately a supply voltage on the first supply voltage node, and the weak latch circuit operable responsive to the second output signal to drive the first output signal on the first complementary output node to approximately a reference voltage on the first reference node; and

a second input signal write circuit coupled between the second complementary output node and the second supply voltage node, the second input signal write circuit configured to receive the second complementary input signal on a second complementary input node and operable in response to the second complementary input signal to cause the strong latch circuit to drive the first output signal on the first complementary output node to approximately the supply voltage on the first supply voltage node, and the weak latch circuit operable responsive to the first output signal to drive the second output signal on the second complementary output node to approximately the reference voltage on the first reference node.

4. The level shifter circuit of claim 3, wherein the strong latch comprises MOS transistors having a first conductivity type and the weak latch comprises MOS transistors having a second conductivity type, the size of the MOS transistors in the strong latch being larger than the size of the MOS transistors in the weak latch.

5. The level shifter circuit of claim 4, wherein the strong latch circuit comprises:

a first MOS transistor having a first signal node coupled to the first supply voltage node, a second signal node coupled to the first complementary output node, and a control node coupled to the second complementary output node; and

a second MOS transistor having a first signal node coupled to the first supply voltage node, a second signal node coupled to the second complementary output node, and a control node coupled to the first complementary output node.

6. The level shifter circuit of claim 5, wherein the weak latch circuit comprises:

a third MOS transistor having a first signal node coupled to the first reference voltage node, a second signal node coupled to the first complementary output node, and a control node coupled to the second complementary output node; and

a fourth MOS transistor having a first signal node coupled to the first reference voltage node, a second signal node coupled to the second complementary output node, and a control node coupled to the first complementary output node.

7. The level shifter circuit of claim 6, wherein each of the first and second input signal write circuits comprises:

a fifth MOS transistor having a first signal node coupled to the second supply voltage node, a second signal node coupled to a first intermediate node, and a control node coupled to the first complementary input node;

a sixth MOS transistor having a first signal node coupled to the first intermediate node, a second signal terminal coupled to a second intermediate node, and a control node coupled to a second reference voltage node;

a seventh MOS transistor having a first signal node coupled to the second intermediate node, a second signal node coupled to the corresponding first or second complementary output node, and a control node coupled to the first reference voltage node;

an eighth MOS transistor having a first signal node coupled to the first intermediate node, a second signal node coupled to the second reference voltage node, and a control node coupled the corresponding first or second complementary input node;

a ninth MOS transistor having a first signal node coupled to the first reference voltage node, a second signal node coupled to the corresponding first or second complementary output node, and a control node coupled to the second intermediate node; and

a capacitor having a first signal node coupled to the corresponding first or second complementary output node and a second signal node coupled to the second intermediate node.

8. The level shifter circuit of claim 7,

wherein the first conductivity type is P-type and the second conductivity type is N-type;

wherein the fifth and sixth MOS transistors are N-type transistors;

wherein the seventh, eighth and ninth transistors are P-type transistors;

wherein the first supply voltage node receives a positive supply voltage VDDE;

wherein the second supply voltage node receives a ground voltage GNDE;

wherein the first reference voltage node receives a second reference voltage VREF2; and

wherein the second reference voltage node receives a first reference voltage VREF1, the magnitude of the first reference voltage VREF1 being greater than or equal to the magnitude of second reference voltage VREF2.

9. The level shifter circuit of claim 7,

wherein the first conductivity type is N-type and the second conductivity type is P-type,

wherein the fifth and sixth MOS transistors are P-type transistors;

wherein the seventh, eighth and ninth transistors are N-type transistors;

wherein the first supply voltage node receives a ground voltage GNDE;

wherein the second supply voltage node receives a positive supply voltage VDDE;

wherein the first reference voltage node receives a first reference voltage VREF1; and

wherein the second reference voltage node receives a second reference voltage VREF2, the magnitude of the first reference voltage VREF1 being greater than or equal to the magnitude of second reference voltage VREF2.

10. A level shifter circuit configured to receive first and second complementary input signals, each of the first and second complementary input signals having a value of either a first voltage or a second voltage, and the level shifter including a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a third voltage and including a weak latch circuit operable in response to the first and second complementary input signals to drive the other of the first and second output signals to a fourth voltage.

11. The level shifter circuit of claim 10, wherein the first voltage is ground, the second voltage is a first positive reference voltage, the third voltage is a second positive reference voltage, and the fourth voltage is a positive supply voltage.

12. The level shifter circuit of claim 11, wherein the first positive reference voltage is equal to or less than the positive supply voltage and wherein the second reference voltage is equal to or greater than ground.

13. The level shifter circuit of claim 11, wherein the second positive reference voltage is less than the first positive reference voltage.

14. The level shifter circuit of claim 11, wherein the positive supply voltage has a value of one of 1.8V, 2.5V, and 3.3V, or any other voltage between 1.8V and 3.3V.

15. A method, comprising:

shifting voltage levels of first and second complementary input signals, each of the first and second complementary input signals having either a first voltage level or a second voltage level, the shifting voltage levels including,

providing a first current to a first output node to drive a first output signal on the first output node to a third voltage level responsive to the first complementary input signal, and

providing a second current to a second output node to drive a second output signal on the second output node to a fourth voltage level responsive to the first output signal, the second current having a magnitude that is higher than a magnitude of the first current.

16. The method of claim 15, further comprising:

providing the first current to the second output node to drive the second output signal on the second output node to the third voltage level responsive to the second complementary input signal, and

providing the second current to the first output node to drive the first output signal on the first output node to the fourth voltage level responsive to the second output signal.

17. The method of claim 16, wherein the first voltage is ground, the second voltage is a first positive reference voltage, the third voltage is a second positive reference voltage, and the fourth voltage is a positive supply voltage.

18. The method of claim 17, wherein the positive supply voltage has a value of one of 1.8V, 2.5V, and 3.3V or any other voltage between 1.8V and 3.3V.

19. The method of claim 16, wherein the fourth voltage is a first positive reference voltage, the first voltage is a second positive reference voltage, the second voltage is a positive supply voltage, and the third voltage is ground.

20. An electronic system, comprising:

a data input device;

a data output device;

a data storage device; and

electronic circuitry coupled to the data input device, data output device, and data storage device, the electronic circuitry comprising at least one integrated circuit including a plurality of input/output buffer circuits, each of the plurality of buffer circuits including at least one level shifter circuit configured to receive first and second complementary input signals, each of the first and second complementary input signals having a value of either a first supply voltage or a first reference voltage and the level shifter further including a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and including a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage.

21. The electronic system of claim 20, wherein the electronic circuitry comprises multiple integrated circuits and the input/output buffer circuits are configured to communicate signals between integrated circuits through the level shifter circuits.

22. The electronic system of claim 21, wherein the multiple integrated circuits utilize different supply voltages.