METHODS AND ARRANGEMENTS FOR DIRECT CURRENT ESTIMATION OF A WIRELESS COMMUNICATION PACKET

• US 20150280862A1
• Filed: 03/28/2014
• Published: 10/01/2015
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Teplitsky, Moshe, Genossar, Michael, Banin, Elan
• Granted Patent: US 9,374,197 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04B 2001/305 using dc offset compensation techniques
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase

Abstract

Logic for direct current (DC) estimation of a wireless communication packet. Logic may determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet. Logic may determine a second DC estimation based upon a second set of sequences in the preamble. Logic may select one of the DC estimations based upon a frequency-offset estimation. Logic may remove one of the DC estimations from the packet. Logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias. And logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.

Claims

1. An apparatus for direct current (DC) estimation of a wireless communication packet, the apparatus comprising:

high frequency offset logic to determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet;

low frequency offset logic to determine a second DC estimation based upon a second set of sequences in the preamble;

selection logic to select one of the DC estimations based upon a frequency offset estimation; and

receiver DC estimation logic to remove the one of the DC estimations from the packet.

2. The apparatus of claim 1, further comprising a processor, a memory coupled with the processor, a radio coupled with the physical layer logic, and one or more antennas coupled with the radio to receive the response.

3. The apparatus of claim 1, further comprising nulling logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias.

4. The apparatus of claim 1, further comprising post equalization logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.

5. The apparatus of claim 1, wherein the first set of sequences comprises a set of short training sequences received after acquisition (ACQ) logic indicates that an analog gain for the sequences is stable.

6. The apparatus of claim 1, wherein the second set of sequences comprises a set of short training sequences received after an ACQ logic detects a boundary of the sequences.

7. The apparatus of claim 1, wherein the second set of sequences comprises a Golay sequence Ga and a Golay sequence −

Ga.

8. One or more tangible computer-readable non-transitory storage media comprising computer-executable instructions operable to, when executed by at least one computer processor, enable the at least one computer processor to implement a method comprising:

determining a first direct current (DC) estimation based upon a first set of sequences in a preamble of a wireless communication packet;

determining a second DC estimation based upon a second set of sequences in the preamble;

selecting one of the DC estimations based upon a frequency offset estimation; and

removing the one of the DC estimations from the packet.

9. The storage media of claim 8, wherein the method further comprises null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias.

10. The storage media of claim 8, wherein the method further comprises determining a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and applying the correction to the packet.

11. The storage media of claim 8, wherein the first set of sequences comprises a set of short training sequences received after acquisition (ACQ) logic indicates that an analog gain for the sequences is stable.

12. The storage media of claim 8, wherein the second set of sequences comprises a set of short training sequences received after ACQ logic detects a boundary of the sequences.

13. The storage media of claim 8, wherein the second set of sequences comprises a Golay sequence Ga and a Golay sequence −

Ga.

15. The method of claim 13, further comprising nulling DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias.

16. The method of claim 13, further comprising determining a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and applying the correction to the packet.

17. The method of claim 13, wherein the first set of sequences comprises a set of short training sequences received after acquisition (ACQ) logic indicates that an analog gain for the sequences is stable.

18. The method of claim 13, wherein the second set of sequences comprises a set of short training sequences received after ACQ logic detects a boundary of the sequences.

19. The method of claim 13, wherein the second set of sequences comprises a Golay sequence Ga and a Golay sequence −

Ga.

14. A method for direct current (DC) estimation of a wireless communication packet, the method comprising:

determining a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet;

determining a second DC estimation based upon a second set of sequences in the preamble;

selecting one of the DC estimations based upon a frequency offset estimation; and

removing the one of the DC estimations from the packet.

20. A system for direct current (DC) estimation of a wireless communication packet, the system comprising:

a processor;

a memory coupled with the processor;

a physical layer (PHY) logic to determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet;

to determine a second DC estimation based upon a second set of sequences in the preamble;

to select one of the DC estimations based upon a frequency offset estimation; and

to remove the one of the DC estimations from the packet;

a radio; and

one or more antennas coupled with the radio to receive the packet.

21. The apparatus of claim 20, wherein the PHY logic comprises nulling logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias.

22. The apparatus of claim 20, wherein the PHY logic comprises post equalization logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.

23. The apparatus of claim 20, wherein the first set of sequences comprises a set of short training sequences received after acquisition (ACQ) logic indicates that an analog gain for the sequences is stable.

24. The apparatus of claim 20, wherein the second set of sequences comprises a set of short training sequences received after ACQ logic detects a boundary of the sequences.

25. The apparatus of claim 20, wherein the second set of sequences comprises a Golay sequence Ga and a Golay sequence −

Ga.