ELECTRONIC ASSEMBLY THAT INCLUDES STACKED ELECTRONIC COMPONENTS

• US 20150282367A1
• Filed: 03/27/2014
• Published: 10/01/2015
• Est. Priority Date: 03/27/2014
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Barth, Hans-Joachim, Mahnkopf, Reinhard, Albers, Sven, Meyer, Thorsten
• Application Number:
  US14/227,977
• Publication Number:
  US 20150282367A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 13/00 Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
• CPC Class Codes: H05K 2203/06 Lamination
• CPC Class Codes: H05K 3/36 : Assembling printed circuits with other printed circuits H05K7/142 takes precedence
• CPC Class Codes: H05K 7/02 : Arrangements of circuit components or wiring on supporting structure
• CPC Class Codes: H05K 7/023 : Stackable modules
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor

Abstract

An electronic assembly that includes a first electronic component that includes a first substrate having a front side and a back side and at least one electronic assembly mounted on the front side of the first substrate, a second electronic component that includes a second substrate having a front side and a back side and at least one electronic assembly mounted on the front side of the second substrate, and wherein the back side of the first substrate is directly attached to the back side of the second substrate.

Claims

1. An electronic assembly, comprising:

a first electronic component that includes a first substrate having a front side and a back side and at least one electronic device mounted on the front side of the first substrate;

a second electronic component that includes a second substrate having a front side and a back side and at least one electronic device mounted on the front side of the second substrate; and

wherein the back side of the first substrate is directly attached to the back side of the second substrate.

2. The electronic assembly of claim 1, wherein the back side of the first substrate is directly adhered to the back side of the second substrate.

3. The electronic assembly of claim 1, wherein the one electronic device is an active electronic device that is on the front side of the first substrate or the front side of the second substrate.

4. The electronic assembly of claim 1, wherein the one electronic device is a passive electronic device that is on the front side of the first substrate or the front side of the second substrate.

5. The electronic assembly of claim 1, further comprising a third electronic component that includes a third substrate having a front side and a back side and at least one electronic device mounted on the front side of the third substrate, wherein the back side of the third substrate is directly attached to the back side of the first substrate.

6. The electronic assembly of claim 5, wherein at least one of the first substrate, second substrate and third substrate are made of a different material than the rest of the first, second and third substrates.

7. The electronic assembly of claim 1, wherein at least one of the first electronic component and the second electronic component is a die.

8. An electronic package, comprising:

a first electronic component that includes a first substrate having a front side and a back side and at least one electronic device mounted on the front side of the first substrate;

a second electronic component that includes a second substrate having a front side and a back side and at least one electronic device mounted on the front side of the second substrate, wherein the back side of the first substrate is directly attached to the back side of the second substrate to from an electronic assembly; and

a packaging layer, the electronic assembly being embedded within the packing layer to form the electronic package.

9. The electronic package of claim 8, wherein the electronic assembly is embedded entirely within the packaging layer.

10. The electronic package of claim 8, wherein the packaging layer is an embedded wafer level ball grid array.

11. The electronic package of claim 10, wherein the packaging layer includes a plurality of embedded wafer level ball grid arrays.

12. The electronic package of claim 8, further comprising a third electronic component attached to the packaging layer.

13. An electronic system, comprising:

a first electronic package that includes (i) a first electronic component that includes a first substrate having a front side and back side and at least one electronic device mounted on the front side of the first substrate;

(ii) a second electronic component that includes a second substrate having a front side and a back side and at least one electronic device mounted on the front side of the second substrate, wherein the back side of the first substrate is directly attached to the back side of the second substrate to from an electronic assembly; and

(iii) a first packaging layer, the electronic assembly being embedded within the first packing layer to form a first electronic package; and

a second electronic package that includes at least one electronic component, the second electronic assembly being stacked onto or positioned below the first electronic package.

14. The electronic system of claim 13, wherein the second electronic assembly includes a second packaging layer, the second electronic assembly being embedded within the second packing layer to form a second electronic package that is stacked onto or positioned below the first electronic package.

15. The electronic system of claim 13, wherein the second electronic assembly includes (i) a third electronic component that includes a third substrate having a front side and a back side and at least one electronic device mounted on the front side of the third substrate;

(ii) a fourth electronic component that includes a fourth substrate having a front side and a back side and at least one electronic device mounted on the front side of the fourth substrate, wherein the back side of the fourth substrate is directly attached to the back side of the third substrate to from the second electronic assembly; and

(iii) a second packaging layer, the second electronic assembly being embedded within the second packing layer to form a second electronic package that is stacked onto or positioned below the first electronic package.

16. The electronic system of claim 15, wherein the first packaging layer and the second packing layer are different types of packaging layers.

17. The electronic system of claim 15, wherein at least one of the first packaging layer and the second packing layer is a ball grid array laminate.

18. A method, comprising:

providing a first electronic component that includes a first substrate having a front side and a back side and at least one electronic device mounted on the front side of the first substrate;

providing a second electronic component that includes a second substrate having a front side and a back side and at least one electronic device mounted on the front side of the second substrate; and

attaching the back side of the first substrate directly to the back side of the second substrate to form an electronic assembly.

19. The method of claim 18, wherein attaching the back side of the first substrate directly to the back side of the second substrate to form an electronic assembly includes directly adhering the back side of the first substrate to the back side of the second substrate.

20. The method of claim 19, further comprising:

providing a third electronic component that includes a third substrate having a front side and a back side and at least one electronic device mounted on the front side of the third substrate; and

directly attaching the back side of the third substrate to the back side of the first substrate to form the electronic assembly.