FLAT PANEL DISPLAY

• US 20150286325A1
• Filed: 09/11/2014
• Published: 10/08/2015
• Est. Priority Date: 04/08/2014
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Ki Hoon
• Application Number:
  US14/483,419
• Publication Number:
  US 20150286325A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A flat panel display includes: upper and lower substrates, each partitioned into first and second non-display areas at an edge of a display area; sensing patterns in the display area of the upper substrate; sense lines in the first non-display area of the upper substrate and connected with the sensing patterns; a sense pad in the second non-display area of the upper substrate and connected with the sense lines; resistance reducing lines in the first non-display area of the upper substrate and connected with at least some sensing patterns; a sealing member between the upper substrate and the non-display area of the lower substrate; metal patterns in the second non-display area of the lower substrate, overlapping with the sense pad and the sense resistance pads; and a conductive ball area between the sense pad, the resistance reducing pads, and the metal patterns, and including conductive balls.

Claims

1. A flat panel display comprising:

an upper substrate and a lower substrate, each partitioned into a first non-display area and a second non-display area formed at an external edge of a display area;

a plurality of sensing patterns formed in a display area of the upper substrate that faces the lower substrate;

sense lines formed in the first non-display area of the upper substrate and respectively connected with the sensing patterns;

a sense pad formed in the second non-display area of the upper substrate and connected with the sense lines;

resistance reducing lines formed in the first non-display area of the upper substrate and connected with at least a part of the sensing patterns;

a resistance reducing pad formed in the second non-display area of the upper substrate and including resistance reducing pads connected with the resistance reducing lines;

a sealing member formed between the upper substrate and the non-display area of the lower substrate;

metal patterns formed in the second non-display area of the lower substrate, overlapping with the sense pad and the sense resistance pad; and

a conductive ball area provided between the sense pad, the resistance reducing pads, and the metal patterns of the lower substrate and including conductive balls.

2. The flat panel display of claim 1, wherein

the sense pad comprises first connection patterns connected with the sense lines and second connection patterns electrically connected with the metal patterns in the lower substrate, and

the resistance reducing pad comprises third connection patterns connected with the resistance reducing lines and fourth connection patterns electrically connected with the metal patterns in the lower substrate.

3. The flat panel display of claim 2, wherein the sense pad and the resistance reducing pad are connected in parallel to one another.

4. The flat panel display of claim 2, wherein the sense pad and the resistance reducing pad are electrically connected with the metal patterns of the lower substrate through the conductive balls.

5. The flat panel display of claim 4, wherein the conductive ball area is filled with a paste, and the plurality of conductive balls are randomly dispersed in the paste.

6. The flat panel display of claim 5, wherein the plurality of conductive balls include gold (Au).

7. The flat panel display of claim 4, wherein the sealing member and the conductive ball area are separated from each other.

8. The flat panel display of claim 1, wherein the sensing patterns comprise

first sensing cells formed to be connected for each row line along a horizontal direction of the upper substrate and first connection lines connecting the first sensing cells, and

second sensing cells formed to be connected for each column line along a vertical direction of the upper substrate and second connection lines connecting the second sensing cells.

9. The flat panel display of claim 8, wherein sense lines comprise first sense lines connected with the first connection lines and second sense lines connected with the second connection lines, and including at least one of molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), or aluminum (Al).

10. The flat panel display of claim 8, wherein the first sense lines and the second sense lines are provided at a distance from each other in the upper substrate.

11. The flat panel display of claim 8, wherein the second sense line is further layered in the first sense line, and the first sense line is further layered in the second sense line.

12. The flat panel display of claim 1, wherein the resistance reducing pad is formed in at least one side of the upper substrate.

13. The flat panel display of claim 1, wherein a flexible printed circuit board that is electrically connected with the metal patterns is attached to an end of the second non-display area of the lower substrate.

14. The flat panel display of claim 13, wherein the metal patterns are connected with a driving IC mounted to the flexible printed circuit board.

15. The flat panel display of claim 13, wherein a plurality of pixels are formed in the display area of the lower substrate, and signal lines that electrically connect the plurality of pixels with the metal patterns formed in the second non-display area are formed in the first non-display area of the lower substrate.

16. The flat panel display of claim 15, wherein the signal lines comprise scan lines and data lines.

17. The flat panel display of claim 8, wherein a black matrix is further formed in the first non-display area and the second non-display area of the upper substrate so as to be arranged in the edge of the display area.

18. The flat panel display of claim 1, wherein the metal patterns are formed at external edges of the sealing member.

19. A method of manufacturing a flat panel display, the method comprising:

forming an upper substrate and a lower substrate, each partitioned into a first non-display area and a second non-display area formed at an external edge of a display area;

forming a plurality of sensing patterns in a display area of the upper substrate that faces the lower substrate;

forming sense lines in the first non-display area of the upper substrate and respectively connected with the sensing patterns;

forming a sense pad in the second non-display area of the upper substrate and connected with the sense lines;

forming resistance reducing lines in the first non-display area of the upper substrate and connected with at least a part of the sensing patterns;

forming a resistance reducing pad in the second non-display area of the upper substrate and including resistance reducing pads connected with the resistance reducing lines;

forming a seal between the upper substrate and the non-display area of the lower substrate;

forming metal patterns in the second non-display area of the lower substrate, overlapping with the sense pad and the sense resistance pad; and

providing a conductive ball area between the sense pad, the resistance reducing pad, and the metal patterns of the lower substrate and including conductive balls.

20. The method of manufacturing a flat panel display of claim 19, wherein

connection patterns are connected with the sense lines and with second connection patterns electrically connected with the metal patterns in the lower substrate, and

third connection patterns are connected with the resistance reducing lines and fourth connection patterns are electrically connected with the metal patterns in the lower substrate.