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MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE, AND CONTROL METHOD OF MEMORY CONTROLLER

  • US 20150286411A1
  • Filed: 07/16/2014
  • Published: 10/08/2015
  • Est. Priority Date: 04/02/2014
  • Status: Abandoned Application
First Claim
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1. A memory controller configured to control a semiconductor memory, comprising:

  • a first receiver configured to receive a ready/busy signal which is indicative of busy when at least one of a plurality of banks of the semiconductor memory is in a busy state, and is indicative of ready when at least two of the plurality of banks are in a ready state;

    a transmitter configured to send, when the ready/busy signal is indicative of the busy, a status read request inquiring of a bank included in the plurality of banks as to whether the bank is in the ready state or in the busy state;

    a second receiver configured to receive a status signal as a response to the status read request; and

    a request transmitter configured to send a request to a ready-state bank included in the plurality of banks, based on the status signal and the ready/busy signal.

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