MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE, AND CONTROL METHOD OF MEMORY CONTROLLER
First Claim
Patent Images
1. A memory controller configured to control a semiconductor memory, comprising:
- a first receiver configured to receive a ready/busy signal which is indicative of busy when at least one of a plurality of banks of the semiconductor memory is in a busy state, and is indicative of ready when at least two of the plurality of banks are in a ready state;
a transmitter configured to send, when the ready/busy signal is indicative of the busy, a status read request inquiring of a bank included in the plurality of banks as to whether the bank is in the ready state or in the busy state;
a second receiver configured to receive a status signal as a response to the status read request; and
a request transmitter configured to send a request to a ready-state bank included in the plurality of banks, based on the status signal and the ready/busy signal.
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Abstract
According to one embodiment, a memory controller controls a semiconductor memory. The memory controller includes a first receiver, a transmitter, a second receiver, and a request transmitter.
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Citations
18 Claims
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1. A memory controller configured to control a semiconductor memory, comprising:
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a first receiver configured to receive a ready/busy signal which is indicative of busy when at least one of a plurality of banks of the semiconductor memory is in a busy state, and is indicative of ready when at least two of the plurality of banks are in a ready state; a transmitter configured to send, when the ready/busy signal is indicative of the busy, a status read request inquiring of a bank included in the plurality of banks as to whether the bank is in the ready state or in the busy state; a second receiver configured to receive a status signal as a response to the status read request; and a request transmitter configured to send a request to a ready-state bank included in the plurality of banks, based on the status signal and the ready/busy signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A control method of a memory controller configured to control a semiconductor memory, comprising:
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receiving a ready/busy signal which is indicative of busy when at least one of a plurality of banks of the semiconductor memory is in a busy state, and is indicative of ready when at least two of the plurality of banks are in a ready state; sending, when the ready/busy signal is indicative of the busy, a status read request inquiring of a bank included in the plurality of banks as to whether the bank is in the ready state or in the busy state; receiving a status signal as a response to the status read request; and sending a request to a ready-state bank included in the plurality of banks, based on the status signal and the ready/busy signal. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification