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MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT

  • US 20150286761A1
  • Filed: 05/24/2013
  • Published: 10/08/2015
  • Est. Priority Date: 06/01/2012
  • Status: Active Grant
First Claim
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1. Method of designing a prototype comprising several programmable chips such as chips of FPGA type, to model an ASIC circuit, this ASIC circuit being intended to implement logic design comprising a hierarchy of logic modules communicating with one another, this method comprising the steps of:

  • partitioning the hierarchy of logic modules into regions each comprising one or more programmable chips while minimizing;

    on the one hand the inter-region communications in a manner correlated with the physical connections available between each pair of programmable chips;

    and on the other hand the number of traversal(s) of programmable chips of a critical combinatorial path;

    establishing a routing of the signals between programmable chips by using the physical resources available.

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