MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT

• US 20150286761A1
• Filed: 05/24/2013
• Published: 10/08/2015
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Flexras Technologies SAS (Siemens AG)
• Inventors: Marrakchi, Zied, Alexandre, Christophe
• Granted Patent: US 9,400,860 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of: —partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising: —inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; —and the number of crossings of programmable chips of a critical combinatorial path; —establishing a routing of the signals between programmable chips using the physical resources available.

Claims

1. Method of designing a prototype comprising several programmable chips such as chips of FPGA type, to model an ASIC circuit, this ASIC circuit being intended to implement logic design comprising a hierarchy of logic modules communicating with one another, this method comprising the steps of:

partitioning the hierarchy of logic modules into regions each comprising one or more programmable chips while minimizing;

on the one hand the inter-region communications in a manner correlated with the physical connections available between each pair of programmable chips;

and on the other hand the number of traversal(s) of programmable chips of a critical combinatorial path;

establishing a routing of the signals between programmable chips by using the physical resources available.

2. Method according to claim 1, in which modifications are applied in an iterative and automated manner to the partitioning before establishing a new routing and before estimating the operating frequency of the prototype formed by the programmable chips of the said regions by a temporal analysis, until a target frequency is attained.

3. Method according to claim 1, furthermore comprising, prior to the partitioning step, a step of creating a new hierarchy of logic modules on the basis of the hierarchy of the logic modules of the logic design, by flattening the modules that cannot be be preserved, according to design constraints, while implementing the logic design, and in which the partitioning step is applied to this new hierarchy.

4. Method according to claim 1, comprising, prior to the step of establishing a routing of the signals between programmable chips, a step of establishing a routing of the configurable communication links between programmable chips.

5. Method according to claim 1, in which the partitioning is recursive so as to adapt to the hierarchy of the programmable platform, by:

partitioning the hierarchy into regions each having resources limited to the sum of the resources of the programmable chips that it contains;

partitioning the design instances belonging to each region between local programmable chips without authorizing the instances of a programmable chip to move to a programmable chip of a different region.

6. Method according to claim 1, in which the step of establishing a routing of the signals between the programmable chips by using the physical resources available is ensured by representing the resources of the board by a graph in which the nodes are pins of programmable chips and the edges are physical tracks.