MULTI-FPGA PROTOTYPING OF AN ASIC CIRCUIT
First Claim
1. Method of designing a prototype comprising several programmable chips such as chips of FPGA type, to model an ASIC circuit, this ASIC circuit being intended to implement logic design comprising a hierarchy of logic modules communicating with one another, this method comprising the steps of:
- partitioning the hierarchy of logic modules into regions each comprising one or more programmable chips while minimizing;
on the one hand the inter-region communications in a manner correlated with the physical connections available between each pair of programmable chips;
and on the other hand the number of traversal(s) of programmable chips of a critical combinatorial path;
establishing a routing of the signals between programmable chips by using the physical resources available.
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Accused Products
Abstract
The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of: —partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising: —inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; —and the number of crossings of programmable chips of a critical combinatorial path; —establishing a routing of the signals between programmable chips using the physical resources available.
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Citations
6 Claims
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1. Method of designing a prototype comprising several programmable chips such as chips of FPGA type, to model an ASIC circuit, this ASIC circuit being intended to implement logic design comprising a hierarchy of logic modules communicating with one another, this method comprising the steps of:
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partitioning the hierarchy of logic modules into regions each comprising one or more programmable chips while minimizing; on the one hand the inter-region communications in a manner correlated with the physical connections available between each pair of programmable chips; and on the other hand the number of traversal(s) of programmable chips of a critical combinatorial path; establishing a routing of the signals between programmable chips by using the physical resources available. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification