SEMICONDUCTOR WAFER AND METHOD OF CONCURRENTLY TESTING CIRCUITS FORMED THEREON
First Claim
Patent Images
1. A semiconductor wafer, comprising:
- a semiconductor substrate;
an array of identical integrated circuits formed on the substrate, wherein each of the circuits has a plurality of bond pads and a plurality of probe pads including at least first and second probe pads;
a plurality of seal rings, each seal ring enclosing a respective one of the integrated circuits;
a first common electrical interconnect that electrically couples together the first probe pads of the integrated circuits of the array; and
a second common electrical interconnect that electrically couples together the second probe pads of the integrated circuits of the array.
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Abstract
A semiconductor wafer has a non-uniform array of integrated circuit dies formed on it. Each die is enclosed by a respective seal ring, and each die has a group of bond pads and probe pad coupled to the bond pads. Common electrical interconnects selectively electrically couple together respective probe pads of each of the dies. The common electrical interconnects allow the dies to be tested concurrently before being cut from the wafer.
20 Citations
20 Claims
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1. A semiconductor wafer, comprising:
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a semiconductor substrate; an array of identical integrated circuits formed on the substrate, wherein each of the circuits has a plurality of bond pads and a plurality of probe pads including at least first and second probe pads; a plurality of seal rings, each seal ring enclosing a respective one of the integrated circuits; a first common electrical interconnect that electrically couples together the first probe pads of the integrated circuits of the array; and a second common electrical interconnect that electrically couples together the second probe pads of the integrated circuits of the array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of testing an array of identical fabricated integrated circuits formed on a semiconductor substrate, each of the integrated circuits being enclosed by a respective seal ring, wherein each of the integrated circuits has a group of bond pads and a plurality of probe pads selectively coupled to the bond pads, wherein there are common electrical interconnects that selectively electrically couple together respective ones of the probe pads on each of the integrated circuits, the method comprising:
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selectively coupling test probes to the probe pads; selectively supplying input test patterns to the test probes to thereby concurrently supply the input test patterns to all of the integrated circuits in the array; and processing output test patterns from the test probes in response to the input test patterns, wherein the output test patterns are received by one or more of the test probes to thereby determine if any of the integrated circuits are faulty. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A assembling a packaged semiconductor die, the method including:
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receiving a semiconductor wafer with an array of identical fabricated integrated circuits formed thereon, wherein each of the integrated circuits is enclosed by a respective seal ring, each of the integrated circuits has a group of bond pads and a plurality of probe pads selectively coupled to the bond pads, wherein there are common electrical interconnects on the wafer that selectively electrically couple together respective ones of the probe pads on each of the integrated circuits, and wherein each of the integrated circuits has at least one die test pad coupled to one of the bond pads, wherein the die test pad is electrically isolated from all of the other integrated circuits; testing concurrently each of the integrated circuits with input test patterns applied to the probe pads to identify which integrated circuits are fault free; cutting at least one of the fault free integrated circuits from the semiconductor wafer to provide a single semiconductor die enclosed by one of the seal rings; electrically connecting the bond pads of the semiconductor die to external package connectors; and enclosing the semiconductor die in a protective housing. - View Dependent Claims (17, 18, 19, 20)
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Specification