NONVOLATILE MEMORY CELL STRUCTURE WITH ASSISTANT GATE

• US 20150287732A1
• Filed: 04/01/2015
• Published: 10/08/2015
• Est. Priority Date: 04/02/2014
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Tsao, Mu-Ying, Chen, Wei-Ren
• Granted Patent: US 9,368,161 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H10B 20/20 : Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 : One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A nonvolatile memory (NVM) cell includes a semiconductor substrate having therein an N well and a P well; a first OD region and a second OD region disposed within the N well; a PMOS select transistor disposed on the first OD region; a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the second OD region and the N well. The select transistor, the floating gate transistor and the assistant gate disposed on the same N well.

Claims

1. A nonvolatile memory (NVM) cell, comprising:

a semiconductor substrate having therein an N well;

a first OD region and a second OD region disposed within the N well;

a PMOS select transistor disposed on the first OD region;

a PMOS floating gate transistor serially connected to the select transistor and being disposed on the on the first OD region, wherein the PMOS floating gate transistor comprises a floating gate overlying the first OD region; and

an assistant gate protruding from one distal end of the floating gate to one edge of the second OD region such that the assistant gate is capacitively coupled to the N well, wherein an induced voltage coupled from the assistant gate is controlled by a bias of the N Well.

2. The NVM cell according to claim 1, wherein the select transistor and the floating gate transistor share the N well.

3. The NVM cell according to claim 1, wherein the select transistor comprises a P⁺ source doping region in the N well, a common P⁺ doping region spaced apart from the P⁺ source doping region, a select gate channel region near a main surface of the semiconductor substrate between the P⁺ source doping region and the common P⁺ doping region, a select gate overlying the select gate channel region, and a gate dielectric layer between the select gate and the select gate channel region.

4. The NVM cell according to claim 3, wherein the P⁺ source doping region is coupled to a source line SL.

5. The NVM cell according to claim 3, wherein the floating gate transistor further comprises the common P⁺ doping region on one side of the floating gate, a P⁺ drain doping region on the other side of the floating gate, a floating gate channel region between the common P⁺ doping region and the P⁺ drain doping region, and a gate dielectric layer between the floating gate and the floating gate channel region.

6. The NVM cell according to claim 5, wherein the P⁺ drain doping region is coupled to a bit line BL.

7. The NVM cell according to claim 1, wherein the floating gate transistor serves as a charge storage element of the NVM cell.

8. The NVM cell according to claim 1, wherein the assistant gate is formed integrally with the floating gate using a single layer of polysilicon.

9. The NVM cell according to claim 1, wherein the assistant gate comprises N⁺ doped polysilicon or P⁺ doped polysilicon.

10. The NVM cell according to claim 1, wherein the assistant gate comprises a horizontal segment that extends continuously from the floating gate along a first direction and is directly connected to the floating gate, wherein the assistant gate further comprises a vertical segment that extends along a second direction\and is directly connected to the horizontal segment.

11. The NVM cell according to claim 1 further comprising a P well disposed within the semiconductor substrate and a third OD region disposed within the P well.

12. The NVM cell according to claim 11 further comprising an erase gate extending continuously from the floating gate and traversing a junction between the N well and the P well.

13. The NVM cell according to claim 12, wherein one distal end of the erase gate overlaps with the third OD region such that the erase gate is capacitively coupled to the third OD region and the P well.