SHIFT REGISTER CIRCUIT
First Claim
1. A shift register circuit, comprising:
- a pull-down circuit;
a pull-down control circuit, electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit;
a driving unit, electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit;
a primary pull-down circuit, electrically connected to the pull-down circuit; and
a gate driver circuit, electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal,wherein the driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.
1 Assignment
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Accused Products
Abstract
A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The pull-down control circuit is electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit. The a driving unit is electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit. The primary pull-down circuit is electrically connected to the pull-down circuit. The gate driver circuit is electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal. The driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.
15 Citations
9 Claims
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1. A shift register circuit, comprising:
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a pull-down circuit; a pull-down control circuit, electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit; a driving unit, electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit; a primary pull-down circuit, electrically connected to the pull-down circuit; and a gate driver circuit, electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal, wherein the driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification