PHASE LOCKED LOOP HAVING DUAL BANDWIDTH AND METHOD OF OPERATING THE SAME

• US 20150288367A1
• Filed: 01/07/2015
• Published: 10/08/2015
• Est. Priority Date: 04/02/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Sung-Jin
• Granted Patent: US 9,438,102 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03J 1/005 in a loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A phase locked loop having a dual bandwidth is disclosed. The phase locked loop divides a loop filter into a zero filter and a pole filter, disposes the zero filter in front of a phase-frequency detector (PFD), and performs high-pass filtering on a voltage-controlled oscillator (VCO) noise with a maximum bandwidth and performs low-pass filtering on a charge pump noise (CP noise) with a minimum bandwidth to divide the VCO noise and the CP noise.

Claims

1. A phase locked loop (PLL), comprising:

a time-difference memory configured to store a first time difference between a reference input signal and a feedback signal;

a first phase-frequency detector configured to generate a first up signal and a first down signal based on a second time difference, which is a current time difference, between the reference input signal and the feedback signal;

a second phase-frequency detector configured to generate a second up signal and a second down signal based on the first time difference received from the time-difference memory;

a first charge pump configured to generate a first charge current and a first discharge current in response to the first up signal and the first down signal;

a second charge pump configured to generate a second charge current and a second discharge current in response to the second up signal and the second down signal;

a pole filter configured to perform filtering on the first charge current, the first discharge current, the second charge current and the second discharge current to generate an oscillation control signal;

a voltage-controlled oscillator (VCO) configured to generate an output signal having a frequency that changes in response to the oscillation control signal; and

a frequency divider configured to divide the frequency of the output signal to generate the feedback signal.

2. The PLL of claim 1, wherein VCO noise of the VCO has a high-pass property at an output node, and charge pump (CP) noise of the first and second charge pumps has a low-pass property at the output node.

3. The PLL of claim 1, wherein the PLL has dual bandwidths comprising a first bandwidth with respect to VCO noise of the VCO and a second bandwidth with respect to charge pump (CP) noise of the first and second charge pumps, the first bandwidth being a broad bandwidth and the second bandwidth being a narrow bandwidth.

4. The PLL of claim 3, wherein the first bandwidth is determined by a loop bandwidth of the PLL, and the second bandwidth is determined by a zero filter.

5. The PLL of claim 4, wherein the zero filter is configured to include the time-difference memory, a time-difference amplifier and a time-difference adder.

6. The PLL of claim 3, wherein, because the PLL has dual bandwidths, a size of a capacitor included in the pole filter decreases and amounts of an output current of the first charge pump and an output current of the second charge pump decrease.

7. The PLL of claim 1 further comprising:

a zero filter for filtering in a time-difference domain.

8. The PLL of claim 7, wherein a transfer function of the zero filter is configured to be represented by (A(1−

Z_T<sup>−

1</sup>)+1) in a Z-domain when an amplifier gain is A and a time-difference function is Z_T<sup>−

1</sup>.

9. The PLL of claim 8, wherein the time-difference function (Z_T⁻

1) is configured to be implemented by a time-difference memory or a time-difference register.

10. The PLL of claim 8, wherein a transfer function of the zero filter is configured to be represented by ((A+1)+(−

A*Z_T<sup>−

1</sup>)), and a gain ratio between A and (A+1) is implemented by a ratio of output currents of the first charge pump and the second charge pump, and a negative gain of −

A is implemented by inverting a polarity of an output pair of the second phase-frequency detector and applying the inverted output pair to the second charge pump.

11. The PLL of claim 8, wherein the time-difference memory having the time-difference function (Z_T⁻

1) is configured to include a delay that delays the reference input signal and the feedback signal.

12. A method of operating a phase locked loop (PLL), the method comprising:

performing filtering using a zero filter in a time-difference domain on a reference input signal and a feedback signal to generate a first signal;

performing filtering using a pole filter on the first signal to generate an oscillation control signal; and

generating an output signal having a frequency that changes in response to the oscillation control signal.

13. The method of claim 12, wherein a transfer function of the zero filter is configured to be represented by (A(1−

Z_T<sup>−

1</sup>)+1) in a Z-domain when an amplifier gain is A and a time-difference function is Z_T<sup>−

1</sup>.

14. The method of claim 12, wherein generating the first signal comprises:

storing a first time difference between a reference input signal and a feedback signal in a time-difference memory;

generating a first up signal and a first down signal based on a second time difference, which is a current time difference, between the reference input signal and the feedback signal;

generating a second up signal and a second down signal based on the first time difference received from the time-difference memory;

generating a first charge current and a first discharge current in response to the first up signal and the first down signal; and

generating a second charge current and a second discharge current in response to the second up signal and the second down signal.

15. The method of claim 14, wherein the generating of the first signal further comprises summing the first charge current, the first discharge current, the second charge current and the second discharge current.

16. A phase locked loop (PLL), comprising:

a time-difference memory configured to store a first time difference between a reference input signal and a feedback signal;

a multiplexer configured to output one of the first time difference received from the time-difference memory and a second time difference that is a current time difference between the reference input signal and the feedback signal;

a phase-frequency detector configured to generate an up signal and a down signal based on an output signal of the multiplexer;

a charge pump configured to generate a charge current and a discharge current in response to the up signal and the down signal;

a controller configured to generate control signals based on the up signal and the down signal, and to control the multiplexer and the charge pump using the control signals;

a pole filter configured to perform filtering on the charge current and the discharge current to generate an oscillation control signal;

a voltage-controlled oscillator (VCO) configured to generate an output signal having a frequency that changes in response to the oscillation control signal; and

a frequency divider configured to divide the frequency of the output signal to generate the feedback signal.

17. The PLL of claim 16, wherein VCO noise of the VCO has a high-pass property at an output node, and charge pump (CP) noise of the charge pump has a low-pass property at the output node.

18. The PLL of claim 16, wherein the PLL has dual bandwidths comprising a first bandwidth with respect to VCO noise of the VCO and a second bandwidth with respect to charge pump (CP) noise of the charge pump, the first bandwidth being a broad bandwidth and the second bandwidth being a narrow bandwidth.

19. The PLL of claim 16, wherein the charge pump comprises a first current source and a second current source, the up signal being applied to the first current source and the down signal being applied to the second current source the charge pump.

20. The PLL of claim 19, wherein the charge pump is controlled using time-division multiplexing.