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PHASE LOCKED LOOP HAVING DUAL BANDWIDTH AND METHOD OF OPERATING THE SAME

  • US 20150288367A1
  • Filed: 01/07/2015
  • Published: 10/08/2015
  • Est. Priority Date: 04/02/2014
  • Status: Active Grant
First Claim
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1. A phase locked loop (PLL), comprising:

  • a time-difference memory configured to store a first time difference between a reference input signal and a feedback signal;

    a first phase-frequency detector configured to generate a first up signal and a first down signal based on a second time difference, which is a current time difference, between the reference input signal and the feedback signal;

    a second phase-frequency detector configured to generate a second up signal and a second down signal based on the first time difference received from the time-difference memory;

    a first charge pump configured to generate a first charge current and a first discharge current in response to the first up signal and the first down signal;

    a second charge pump configured to generate a second charge current and a second discharge current in response to the second up signal and the second down signal;

    a pole filter configured to perform filtering on the first charge current, the first discharge current, the second charge current and the second discharge current to generate an oscillation control signal;

    a voltage-controlled oscillator (VCO) configured to generate an output signal having a frequency that changes in response to the oscillation control signal; and

    a frequency divider configured to divide the frequency of the output signal to generate the feedback signal.

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