DIGITAL PHASE LOCKED LOOP FOR LOW JITTER APPLICATIONS

• US 20150288370A1
• Filed: 04/04/2014
• Published: 10/08/2015
• Est. Priority Date: 04/04/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: DENG, Jingdong, MALLADI, Ramana M., HO, Chung S., FLYE, David, JIN, Zhenrong
• Granted Patent: US 9,455,728 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

Claims

1. A phase locked loop circuit, comprising

a ring oscillator;

a digital path including a digital phase detector;

an analog path including a linear phase detector; and

a feedback path connecting an output of the ring oscillator to the digital path and to the analog path,

wherein;

the digital path and the analog path are parallel paths;

the digital path provides a digital tuning signal to the ring oscillator that digitally controls a frequency of the ring oscillator; and

the analog path provides an analog tuning signal to the ring oscillator that continuously controls the frequency of the ring oscillator.

2. The phase locked loop circuit of claim 1, wherein:

the linear phase detector generates the analog tuning signal based on a phase difference between a reference signal and the output of the ring oscillator; and

the ring oscillator includes one or more devices that control the frequency of the ring oscillator based on the analog tuning signal.

3. The phase locked loop circuit of claim 2, wherein:

the ring oscillator includes a ring oscillator array comprising a plurality of oscillator elements; and

the one or more devices selectively activate one or more of the plurality of oscillator elements based on the analog tuning signal.

4. The phase locked loop circuit of claim 3, wherein the one or more devices are one or more varactors connected to one or more of the plurality of oscillator elements.

5. The phase locked loop circuit of claim 3, wherein the one or more devices are one or more current-starved inverters connected to one or more of the plurality of oscillator elements.

6. The phase locked loop circuit of claim 1, wherein the ring oscillator comprises a plurality of oscillator elements and a plurality of resistor devices connected in series.

7. The phase locked loop circuit of claim 6, wherein:

the plurality of resistor devices are comprised of respective voltage-controlled resistors connected between adjacent oscillator elements of the plurality of oscillator elements; and

control inputs of the voltage-controlled resistors are connected to the analog tuning signal.

8. The phase locked loop circuit of claim 6, wherein:

the plurality of resistor devices are comprised of respective pluralities of parallel resistance devices connected between adjacent oscillator elements of the plurality of oscillator elements; and

the ring oscillator further comprises an integral control device that selectively connects individual switchable resistance devices of the pluralities of parallel resistance devices based on the digital tuning signal.

9. The phase locked loop circuit of claim 1, wherein:

the ring oscillator comprises a ring oscillator array comprised of a plurality of oscillator elements; and

the plurality of oscillator elements are one of;

inverters, stacked inverters, capacitors, and resistors.

10. A ring oscillator comprising:

oscillator elements;

a digitally-controlled portion configured to change frequency based on a digital input; and

a proportionally-controlled portion configured to change frequency based on an analog input,

wherein the digital input and analog input are parallel inputs of the ring oscillator.

11. The ring oscillator of claim 10, wherein the analog portion comprises one or more devices that control the frequency of the ring oscillator based on an analog tuning signal.

12. The ring oscillator of claim 11, wherein the one or more devices are varactors.

13. The ring oscillator of claim 11, wherein the one or more devices are current-starved inverters.

14. The ring oscillator of claim 11, wherein the one or more devices are voltage-controlled resistors.

15. The ring oscillator of claim 10, wherein the digitally-controlled portion includes control logic that selectively activates a plurality of the oscillator elements.

16. A method in a computer-aided design system for generating a functional design model of a ring oscillator, said method comprising:

generating a functional representation of an array of oscillator elements;

generating a functional representation of a digitally-controlled device connected to the array and configured to selectively activate a plurality of the oscillator elements based on a digital tuning signal; and

generating a functional representation of one or more proportionally-controlled devices connected to the array and configured to change frequency continuously based on an analog tuning input.

17. The method of claim 16, wherein the proportionally-controlled devices are varactors.

18. The method of claim 16, wherein the proportionally-controlled devices are current-starved inverters.

19. The method of claim 16, wherein the proportionally-controlled devices are voltage-controlled resistors.

20. The method of claim 16, wherein the array of oscillator elements is comprised of one of:

inverters, stacked inverters, capacitors, and resistors.