MEMORY TIMING CIRCUIT

• US 20150294700A1
• Filed: 04/10/2014
• Published: 10/15/2015
• Est. Priority Date: 04/10/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Jefremow, Mihail, Backhausen, Ulrich, Kern, Thomas
• Granted Patent: US 9,281,032 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.

Claims

1. A memory circuit, comprising:

a memory cell configured to provide a charge, voltage, or current to an associated bit-line;

a sense amplifier configured to sense the charge, voltage, or current on the bit-line;

a word-line circuit configured to control a word-line of the memory cell;

a bit-line circuit having at least one of (i) a bit-line voltage control circuit and (ii) a mux circuit; and

a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control at least one of;

(i) the word-line circuit, and (ii) bit-line circuit.

2. The memory circuit of claim 1, wherein the tracking circuit comprises:

a reference sense amplifier;

a reference bit-line; and

a reference element configured to provide a reference charge, voltage, or current to the reference bit-line, wherein the reference sense amplifier and the reference bit-line have a configuration substantially similar to the bit-line and sense amplifier.

3. The memory circuit of claim 2, wherein the reference element is one of (i) a reference memory cell and (ii) reference current generator configured to generate a fixed adjustable reference current.

4. The memory circuit of claim 1, wherein the one or more conditions include at least one of (i) temperature, (ii) voltage, and (iii) a process variation of the memory circuit.

5. The memory circuit of claim 1, wherein the timing control signal is operative to indicate that a sensing operation by the sense amplifier is complete.

6. The memory circuit of claim 2, wherein the reference sense amplifier is configured to indicate a ready state via the timing control signal upon determining that the charge, voltage, or current on the reference bit-line is above a predetermined threshold.

7. The memory circuit of claim 1, wherein:

the word-line circuit comprises at least one of (i) a voltage control circuit, (ii) a word-line address decoder circuit, and (iii) a word-line driver, and

at least one of (i) a word-line voltage control circuit, (ii) a word-line address decode circuit, and (iii) a word-line driver is configured to turn OFF or go to a low power state upon identifying the ready state via the timing control signal.

8. The memory circuit of claim 1, wherein at least one of (i) the bit-line voltage control circuit and (ii) the mux of the bit line circuit is configured to turn OFF or go to low power state, upon identifying the ready state via the timing control signal.

9. The memory circuit of claim 8, further comprising a sense amplifier bias circuit configured to turn OFF or go to low power state, upon identifying the ready state via the timing control signal.

10. The memory circuit of claim 1, wherein:

the sense amplifier comprises a local sense amplifier bias circuit, and

the sense amplifier is configured to locally control its local sense amplifier bias circuit by turning the local sense amplifier bias circuit OFF or placing it in low power state, upon determining that the charge, voltage, or current on the bit-line is above a predetermined threshold.

11. A memory circuit, comprising:

a memory cell configured to provide a charge, voltage, or current to an associated bit-line;

a word-line circuit configured to control a word-line of the memory cell;

a bit-line circuit having at least one of (i) a bit-line voltage control circuit and (ii) a mux circuit; and

a sense amplifier comprising a local sense amplifier bias circuit, wherein the sense amplifier is configured to sense the charge, voltage, or current on the bit-line and locally control its local sense amplifier bias circuit by turning the local sense amplifier bias circuit OFF or placing it in low power state, upon determining that the charge, voltage, or current on the bit-line is above a predetermined threshold.

12. A method of controlling a memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line, a bit-line circuit, a sense amplifier configured to sense the charge, voltage, or current on the bit-line, a word-line circuit configured to control a word-line of the memory cell, and a tracking circuit, the method comprising:

tracking one or more conditions of the bit-line of the memory circuit by the tracking circuit; and

providing a timing control signal to at least one of (i) the word-line circuit and (ii) bit-line circuit of the memory circuit to adaptively control the word-line circuit based on the tracking.

13. The method of claim 12, further comprising adaptively changing the timing control signal based on the one or more conditions, wherein the conditions include at least one of (i) temperature, (ii) voltage, and (iii) a process variation of the memory circuit.

14. The method of claim 13, wherein the timing control signal indicates that a sensing operation of the sense amplifier is complete upon the tracking circuit determining that the charge, current, or voltage on a reference bit-line of the tracking circuit is above a predetermined threshold.

15. The method of claim 13, further comprising turning OFF at least one of (i) a word-line voltage control circuit, (ii) a word-line address decoder circuit, and (iii) a word-line driver of the memory circuit upon the tracking circuit determining that the sensing operation of the sense amplifier is complete.

16. The method of claim 13, further comprising turning OFF or transitioning to a low power state at least one of (i) the bit-line voltage control circuit and (ii) a mux circuit associated with the sense amplifier, upon the tracking circuit determining that the sensing operation of the sense amplifier is complete.

17. The method of claim 13, further comprising turning OFF or transitioning to a low power state a sense amplifier bias circuit based upon the timing control signal.

18. The method of claim 12, further comprising locally controlling a local sense amplifier bias circuit by the sense amplifier by turning the local sense amplifier bias circuit OFF or placing it in low power state, upon determining that charge, voltage, or current on the bit-line is above a predetermined threshold.