MEMORY DEVICES AND METHODS OF OPERATING THE SAME

• US 20150294724A1
• Filed: 01/26/2015
• Published: 10/15/2015
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Kyung-Min Kang, Sang-Wan Nam
• Inventors: NAM, Sang-wan, KANG, Kyung-min
• Granted Patent: US 9,721,664 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

According to example embodiments, a memory device includes a memory cell array, a controller including a normal program controller and a dummy program controller, and a driver. The memory cell array includes a first memory block on a substrate. The first memory block includes a plurality of cell strings on the substrate extending in a vertical direction. The normal program controller is configured to generate a first control signal for programming normal cells of a selected cell string that is selected based on an address received by the controller. The dummy program controller is configured to generate a second control signal for programming at least one dummy cell included in each of the plurality of cell strings before generation of the first control signal. The driver is configured to apply a first operation voltage set for programming the normal cells of the selected cell string to the first memory block in response to the first controller signal. The driver is configured to apply a second operation voltage set for programming the at least one dummy cell to the first memory block in response to the second control signal.

Claims

1. A memory device comprising:

a three-dimensional memory cell array including a first memory block on a substrate, the first memory block including a plurality of cell strings on the substrate, the plurality of cell strings extending in a vertical direction that is perpendicular to the substrate;

a controller including a normal program controller and a dummy program controller,

the normal program controller being configured to generate a first control signal for programming normal cells of a selected cell string among the plurality of cell strings that is selected based on an address received by the controller, and

the dummy program controller being configured to generate a second control signal for programming at least one dummy cell included in each of the plurality of cell strings before the normal program controller generates the first control signal; and

a driver,

the driver being configured to apply a first operation voltage set for programming the normal cells of the selected cell string to the first memory block in response to receiving the first control signal from the controller, and

the driver being configured to apply a second operation voltage set for programming the at least one dummy cell to the first memory block in response to receiving the second control signal from the controller.

2. The memory device of claim 1, wherein

the dummy program controller is configured to generate the second control signal prior to the normal program controller generating the first control signal in response to the controller receiving a program command, and

the program command instructs the controller to program the normal cells of the selected cell string.

3. The memory device of claim 1, wherein the dummy program controller is configured to generate the second control signal after an erasure of the first memory block regardless of whether the controller receives a program command.

4. The memory device of claim 1, wherein

the dummy program controller is configured to generate the second control signal such that the second control signal corresponds to programming the at least one dummy cell by a hot carrier injection (HCl) mechanism to increase a threshold voltage of the at least one dummy cell,

the driver is configured to apply the second operation voltage set to the first memory block for programming the at least one dummy cell by the HCl mechanism in response to receiving the second control signal, and

applying the second operation voltage set includes applying a ground voltage to a string selection transistor and a ground selection transistor in each of the plurality of cell strings, applying a first pass voltage to a first dummy cell connected in series to the string selection transistor and a second dummy cell connected in series to the ground selection transistor, and applying a second pass voltage to the normal cells connected in series between the first dummy cell and the second dummy cell.

5. The memory device of claim 1, wherein

the dummy program controller is configured to generate the second control signal such that the second control signal corresponds to programming the at least one dummy cell by a Fowler-Nordheim (F-N) tunneling mechanism to increase a threshold voltage of the at least one dummy cell,

the driver is configured to apply the second operation voltage set to the first memory block for programming the at least one dummy cell by the F-N tunneling mechanism in response to receiving the second control signal, and

applying the second operation voltage set includes applying a first voltage to a string selection transistor included in each of the plurality of cell strings, applying a ground voltage to a ground selection transistor included in each of the plurality of cell strings, applying a program voltage to a first dummy cell connected in series to the string selection transistor, applying a first pass voltage to a second dummy cell connected in series to the ground selection transistor, and applying a second pass voltage to the normal cells connected in series between the first dummy cell and the second dummy cell.

6. The memory device of claim 1, wherein

the driver is configured to increase a threshold voltage of the at least one dummy cell of at least one cell string among the plurality of cell strings by programming the at least one dummy cell using a Fowler-Nordheim (F-N) tunneling mechanism in response to receiving the second control signal, and

a threshold voltage of the at least one string selection transistor or at least one ground selection transistor in the at least one cell string is lower than a first reference voltage.

7. A method of operating a memory device including a first memory block having a plurality cell strings, each of the plurality of cell strings including a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor, the method comprising:

programming the first dummy cell; and

programming the normal cells in at least one of the plurality of cell strings after the programming the first dummy cell, the normal cells being selected based on a first program command inputted to the memory device.

8. The method of claim 7, wherein the programming the first dummy cell is performed in response to the first program command or the programming the first dummy cell is performed after performing an erasure operation on the first memory block regardless of the first program command being input to the memory device.

9. The method of claim 7, wherein the programming the first dummy cell includes:

programming the first dummy cell;

applying a ground voltage to the string selection transistors and the ground selection transistors;

applying a first pass voltage to the first and second dummy cells; and

applying a second pass voltage to the plurality of normal cells.

10. The method of claim 7, wherein the programming the first dummy cell includes:

applying a first voltage to the string selection transistors;

applying a ground voltage to the ground selection transistors;

applying a program voltage to the first dummy cells; and

applying a pass voltage to the second dummy cells and the plurality of normal cells.

11. The method of claim 10, wherein

each of the plurality of cell strings further includes a third dummy cell between the string selection transistor and the first dummy cell,

each of the plurality of cell strings further includes a fourth dummy cell between the ground selection transistor and the second dummy cell;

and

the programming the first dummy cell further includes applying a voltage lower than the pass voltage to the third and fourth dummy cells.

12. The method of claim 7, wherein the programming the first dummy cell is selectively performed on at least one cell string if at threshold voltage of the string selection transistor or the ground selection transistor in the at least one cell string is lower than a first reference voltage.

13. The method of claim 7, wherein

the programming the first dummy cell is performed at least twice before the normal cells are programmed, and

the number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the plurality of normal cells.

14. The method of claim 7, further comprising:

erasing the first memory block after the normal cells are programmed; and

reprogramming the first dummy cell, wherein the reprogramming of the first dummy cell is performed using a voltage different from the program voltage which is applied to the first dummy cell in programming the first dummy cell.

15. The method of claim 14, further comprising:

programming the normal cells in at least one cell string selected by a second program command additionally inputted to the memory device after the first dummy cells are reprogrammed,

wherein the programming of the normal cells in the at least one cell string selected by the second program command is performed using a voltage different from the voltage that is used in the programming the normal cells of the at least one cell string selected by the first program command.

16. A method of operating a memory device, the memory device including a memory cell array, a controller, and a driver, the method comprising:

increasing a threshold voltage of at least one dummy cell in at least one of a plurality of cell strings in a selected memory block of the memory cell array,

each of the plurality of cell strings including a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor; and

programming the plurality of normal cells in a selected string among the plurality of cell strings after the increasing the threshold voltage of the at least one dummy cell.

17. The method of claim 16, wherein

the increasing the threshold voltage of the at least one dummy cell includes using one of a hot carrier injection (HCl) mechanism and a Fowler-Nordheim (F-N) tunneling mechanism to program the at least one dummy cell before the programming the plurality of normal cells, and

the at least one dummy cell includes the first dummy cell and the second dummy cell in the at least one of the plurality of cell strings.

18. The method of claim 17, wherein

the HCl mechanism is used during the increasing the threshold voltage of the at least one dummy cell, and

the HCl mechanism includes,

turning the string selection transistor and the ground selection transistor off in the at least one of the plurality of cell strings,

applying a first pass voltage to the first dummy cell and the second dummy cell in the at least one of the plurality of cell strings, and

applying a second pass voltage to the plurality of normal cells in the at least one of the plurality of cell strings, wherein

the second pass voltage is greater than the first pass voltage.

19. The method of claim 18,

the F-N tunneling mechanism is used during the increasing the threshold voltage of the at least one dummy cell, and

the F-N tunneling mechanism includes

turning the ground selection transistor off in the at least one of the plurality of cell strings,

applying a first voltage to the string selection transistor in the at least one of the plurality of cell strings,

applying a program voltage to the first dummy cell in the at least one of the plurality of cell strings,

applying a first pass voltage to the second dummy cell in the at least one of the plurality of cell strings, and

applying a second pass voltage to the plurality of normal cells in the at least one of the plurality of cell strings, wherein

a value of the first pass voltage is greater than a value of a ground voltage and less than a value of the program voltage,

a value of the second pass voltage is greater than the value of the ground voltage and less than the value of the program voltage, and

the first voltage is a power supply voltage.

20. The method of claim 16, wherein,

in each of the plurality of cell strings, the second dummy cell is on the ground selection transistor, the plurality of normal cells are on the second dummy cell, the first dummy cell is on the plurality of normal cells, and the string selection transistor is on the first dummy cell,

the programming the plurality of normal cells in the selected string is performed in response to a program command received by the controller, a control signal generated by the controller and transferred to the driver in response to the program command, and an address decoded by the driver,

the programming the plurality of normal cells in the selected string includes the driver applying an operation voltage set to the selected string in response to the control signal transferred to the driver by the controller, and

the increasing the threshold voltage of the at least one dummy cell is performed in response in the controller receiving the programming command, or

the increasing the threshold voltage of the at least one dummy cell is performed after performing an erasure operation on the memory block regardless of the controller receiving the programming command.