SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20150294873A1
• Filed: 03/03/2015
• Published: 10/15/2015
• Est. Priority Date: 04/15/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Wandon, HYUN, Sangjin, LEE, Huyong, KIM, Jae-Jung
• Application Number:
  US14/636,257
• Publication Number:
  US 20150294873A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Provided is a method of fabricating a semiconductor device, including forming an interlayered insulating layer having an opening, on a substrate; sequentially forming a first conductive pattern, a barrier pattern, and a second conductive pattern on bottom and side surfaces of the opening; and nitrifying an upper portion of the second conductive pattern to form a metal nitride layer that is spaced apart from the first conductive pattern.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming, on a substrate, an interlayered insulating layer having an opening;

sequentially forming a first conductive pattern, a barrier pattern, and a second conductive pattern on bottom and side surfaces of the opening; and

nitrifying an upper portion of the second conductive pattern to form a metal nitride layer spaced apart from the first conductive pattern.

2. The method as claimed in claim 1, wherein the metal nitride layer contains a different metallic element from one contained in the first conductive pattern.

3. The method as claimed in claim 1, wherein forming the first conductive pattern, the barrier pattern, and the second conductive pattern includes:

conformally forming a first conductive layer on a top surface of the interlayered insulating layer and on the bottom and side surfaces of the opening;

conformally forming a barrier layer on the first conductive layer; and

forming a second conductive layer on the barrier layer to fill the opening.

4. The method as claimed in claim 3, wherein forming the first conductive pattern, the barrier pattern, and the second conductive pattern further includes planarizing the first conductive layer, the barrier layer, and the second conductive layer to expose the interlayered insulating layer.

5. The method as claimed in claim 1, wherein:

nitrifying the upper portion of the second conductive pattern includes nitrifying an upper portion of the first conductive pattern to form a work-function metal nitride layer, and

the work-function metal nitride layer contains a different material from the metal nitride layer.

6. The method as claimed in claim 5, wherein the work-function metal nitride layer is spaced apart from the metal nitride layer.

7. The method as claimed in claim 1, further comprising forming a gate insulating layer between the first conductive pattern and the opening.

8. The method as claimed in claim 1, further comprising forming an oxide layer on the metal nitride layer, wherein the first conductive pattern has a work function ranging from 4.1 eV to 5.1 eV, after the oxide layer is formed.

9. The method as claimed in claim 1, wherein nitrifying the upper portion of the second conductive pattern includes nitrifying an upper portion of the interlayered insulating layer to form an insulating nitride layer.

10. A semiconductor device, comprising:

a substrate;

an interlayered insulating layer on the substrate and having an opening; and

a gate electrode in the opening, the gate electrode including;

a first conductive pattern on bottom and side surfaces of the opening;

a second conductive pattern on the first conductive pattern;

a metal nitride layer spaced apart from the first conductive pattern, on the second conductive pattern; and

a barrier layer between the first and second conductive patterns.

11. The device as claimed in claim 10, wherein:

the second conductive contains a different material from the first conductive pattern; and

the metal nitride layer contains a same metal material as the second conductive pattern.

12. The device as claimed in claim 11, wherein the metal nitride layer contains a different metallic element from one contained in the first conductive pattern.

13. The device as claimed in claim 11, further comprising a work-function metal nitride layer on the first conductive pattern and spaced apart from the metal nitride layer.

14. The device as claimed in claim 13, wherein the work-function metal nitride layer is thinner than the metal nitride layer.

15. The device as claimed in claim 11, wherein the first conductive pattern has a work function ranging from 4.1 eV to 5.1 eV.

16. The device as claimed in claim 11, further comprising a gate insulating layer between the opening and the first conductive pattern.

17. A method of preventing impurities from infiltrating into a first conductive pattern from a second conductive pattern, the method comprising:

forming the first conductive pattern and the second conductive pattern;

nitrifying a portion of the second conductive pattern to form a metal nitride layer; and

depositing an oxide layer on the metal nitride layer.

18. The method as claimed in claim 17, wherein the metal nitride layer is interposed between the oxide layer and a portion of the second conductive pattern that is not nitrified.

19. The method of claim 17, wherein depositing the oxide layer on the metal nitride layer includes depositing the oxide layer on an exposed portion of the first conductive pattern.

20. The method of claim 17, wherein the metal nitride layer prevents a portion of the second conductive pattern that is not nitrified from being oxidized during depositing of the oxide layer.