SYSTEMS AND METHODS FOR FABRICATING VERTICAL-GATE-ALL-AROUND TRANSISTOR STRUCTURES

• US 20150295040A1
• Filed: 04/14/2014
• Published: 10/15/2015
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: TSAI, TENG-CHUN, LIN, CHENG-TUNG, WANG, LI-TING, CHEN, DE-FANG, LIN, HUAN-JUST
• Granted Patent: US 10,026,658 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/3247 for altering the shape, e.g. smoothing the surface
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Systems and methods are provided for fabricating nanowire devices on a substrate. A first nanowire and a second nanowire are formed on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate. A first source region and a first drain region are formed with n-type dopants, the first nanowire being disposed between the first source region and the first drain region. A second source region and a second drain region are formed with p-type dopants, the second nanowire being disposed between the second source region and the second drain region.

Claims

1. A method for fabricating nanowire devices on a substrate, the method comprising:

forming a first nanowire and a second nanowire on a substrate, the first nanowire and the second nanowire extending substantially vertically relative to the substrate;

forming a first source region and a first drain region with n-type dopants, the first nanowire being disposed between the first source region and the first drain region; and

forming a second source region and a second drain region with p-type dopants, the second nanowire being disposed between the second source region and the second drain region.

2. The method of claim 1, wherein forming the first nanowire and the second nanowire on the substrate includes:

forming a shallow-trench-isolation structure; and

removing part of the substrate to form the first nanowire and the second nanowire, the shallow-trench-isolation structure being between the first nanowire and the second nanowire.

3. The method of claim 1, wherein forming the first nanowire and the second nanowire on the substrate includes:

removing part of the substrate to form the first nanowire and the second nanowire; and

forming a shallow-trench-isolation structure between the first nanowire and the second nanowire.

4. The method of claim 1, wherein:

the first source region is formed through ion implantation at a first time; and

the first drain region is formed through ion implantation at a second time, the second time being different from the first time.

5. The method of claim 1, wherein:

the second source region is formed through ion implantation at a first time; and

the second drain region is formed through ion implantation at a second time, the second time being different from the first time.

6. The method of claim 1, wherein;

the first source region and the first drain region are formed through ion implantation at a first time; and

the second source region and the second drain region are formed through ion implantation at a second time, the second time being different from the first time.

7. The method of claim 1, further comprising:

performing ion implantation on a first channel region in the first nanowire; and

performing ion implantation on a second channel region in the second nanowire.

8. The method of claim 1, further comprising:

forming first contact regions on the first source region and the first drain region; and

forming second contact regions on the second source region and the second drain region.

9. The method of claim 8, further comprising:

forming a metal-containing material on the first source region, the second source region, the first drain region and the second drain region;

forming a cap layer on the metal-containing material; and

annealing the cap layer and the metal-containing material to form the first contact regions and the second contact regions.

10. The method of claim 1, further comprising:

forming a first dielectric material on the first nanowire, the first dielectric material surrounding at least part of the first nanowire; and

forming a second dielectric material on the second nanowire, the second dielectric material surrounding at least part of the second nanowire.

11. The method of claim 10, further comprising:

forming a dielectric material on the first nanowire and the second nanowire, the dielectric material surrounding at least part of the first nanowire and the second nanowire.

12. The method of claim 1, further comprising:

forming one or more third nanowires on the substrate, the third nanowires extending substantially vertically relative to the substrate;

wherein the one or more third nanowires and the first nanowire are used to fabricate a n-type transistor.

13. The method of claim 1, further comprising:

forming one or more fourth nanowires on the substrate, the fourth nanowires extending substantially vertically relative to the substrate;

wherein the one or more fourth nanowires and the second nanowire are used for fabricating a p-type transistor.

14. A structure comprising:

a first nanowire formed on a substrate, the first nanowire extending substantially vertically relative to the substrate;

a first source region including first n-type dopants;

a first drain region including second n-type dopants, the first nanowire being disposed between the first source region and the first drain region;

a second nanowire formed on the substrate, the second nanowire extending substantially vertically relative to the substrate;

a second source region including first p-type dopants; and

a second drain region including second p-type dopants, the second nanowire being disposed between the second source region and the second drain region.

15. The structure of claim 14, further comprising:

a first dielectric material formed on the first nanowire and surrounding at least part of the first nanowire; and

a second dielectric material formed on the second nanowire and surrounding at least part of the second nanowire.

16. The structure of claim 15, further comprising:

a first gate contact material formed on the first dielectric material; and

a second gate contact material formed on the second dielectric material.

17. The structure of claim 14, further comprising:

first contact regions formed on the first source region and the first drain region; and

second contact regions formed on the second source region and the second drain region.

18. The structure of claim 14, further comprising:

one or more third nanowires extending substantially vertically relative to the substrate;

wherein the one or more third nanowires and the first nanowire are included in a n-type transistor.

19. The structure of claim 14, further comprising:

one or more fourth nanowires extending substantially vertically relative to the substrate;

wherein the one or more fourth nanowires and the second nanowire are included in a p-type transistor.

20. A device comprising:

a n-type transistor including;

a first source region in contact with a first end of one or more first nanowires formed on a substrate, the first end being associated with a first height relative to the substrate, the first nanowires extending substantially vertically relative to the substrate;

a first drain region in contact with a second end of the first nanowires, the second end being associated with a second height relative to the substrate, the second height being different from the first height; and

a first channel region in the first nanowires configured to conduct a first current between the first source region and the first drain region; and

a p-type transistor including;

a second source region in contact with a third end of one or more second nanowires formed on the substrate, the third end being associated with a third height relative to the substrate, the second nanowires extending substantially vertically relative to the substrate;

a second drain region in contact with a fourth end of the second nanowires, the fourth end being associated with a fourth height relative to the substrate, the fourth height being different from the third height; and

a second channel region in the second nanowires configured to conduct a second current between the second source region and the second drain region.