CRYSTALLINE MULTIPLE-NANOSHEET STRAINED CHANNEL FETS AND METHODS OF FABRICATING THE SAME

• US 20150295084A1
• Filed: 06/03/2015
• Published: 10/15/2015
• Est. Priority Date: 11/01/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Obradovic, Borna J., Bowen, Robert C., Rodder, Mark S.
• Granted Patent: US 9,570,609 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Claims

1. A field effect transistor, comprising:

a nanosheet stack comprising a plurality of individually gated conduction channels, the individually gated conduction channels respectively comprising a crystalline semiconductor channel layer, a crystalline dielectric layer on the channel layer, and a crystalline semiconductor gate layer on the gate dielectric layer opposite the channel layer, wherein the nanosheet stack is strained from lattice mismatch between ones of the layers thereof.

2. The field effect transistor of claim 1, wherein the crystalline channel layer, the crystalline dielectric layer, and the crystalline gate layer comprise heteroepitaxial layers.

3. The field effect transistor of claim 1, wherein the field effect transistor is an n-type device, and wherein the crystalline channel layer comprises silicon (Si).

4. The field effect transistor of claim 1, wherein the field effect transistor is a p-type device, and wherein the crystalline channel layer comprises silicon germanium (SiGe).

5. The field effect transistor of claim 1, wherein the crystalline dielectric layer comprises calcium fluoride (CaF₂), zinc sulfide (ZnS), praseodymium oxide (Pr₂O₃), and/or gadolinium oxide (Gd₂O₃).

6. The field effect transistor of claim 1, wherein the field effect transistor is an n-type device, and wherein the crystalline gate layer comprises doped silicon germanium (SiGe).

7. The field effect transistor of claim 1, wherein the field effect transistor is a p-type device, and wherein the crystalline gate layer comprises doped silicon (Si).

8. A field effect transistor, comprising:

a body layer comprising a crystalline semiconductor channel region; and

a gate stack on the channel region, the gate stack comprising a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region.

9. The field effect transistor of claim 8, wherein an interface between the channel region and the gate stack is free of amorphous materials.

10. The field effect transistor of claim 9, wherein the gate dielectric layer comprises a high-k crystalline insulating layer directly on the channel region.

11. The field effect transistor of claim 10, wherein the gate layer is directly on the gate dielectric layer, and wherein the channel region and the gate layer comprise heteroepitaxial strained semiconductor layers.

12. The field effect transistor of claim 11, wherein the channel region and the gate layer comprise different Group IV materials, and wherein the gate layer is heavily doped relative to the channel region.

13. The field effect transistor of claim 12, wherein one of the channel region and the gate layer comprises compressively strained silicon germanium (SiGe), and another of the channel region and the gate layer comprises tensile strained silicon (Si).

14. The field effect transistor of claim 11, wherein the gate layer comprises respective crystalline semiconductor gate layers on opposing surfaces of the channel region, and wherein the gate dielectric layer comprises respective crystalline gate dielectric layers between the respective gate layers and the opposing surfaces of the channel region.

15. The field effect transistor of claim 14, wherein a structure comprising the gate stack and the body layer is repeatedly stacked to define a plurality of individually-gated channel regions, and wherein strain in the channel regions and the gate layers is maintained throughout the structure.

16. The field effect transistor of claim 15, wherein the structure has a width of greater than about 30 nanometers but less than about 100 nanometers.

17. The field effect transistor of claim 15, wherein the respective gate layers on the opposing surfaces of the channel region comprise primary gate layers, and further comprising:

a secondary gate layer on sidewalls of the channel region between the opposing surfaces thereof,

wherein the secondary gate layer comprises a metal or doped polycrystalline material.

18. The field effect transistor of claim 17, wherein the plurality of individually-gated channel regions define a fin protruding from a substrate, and wherein the secondary gate layer extends on opposing sidewalls of the fin and on a surface therebetween.

19. The field effect transistor of claim 17, further comprising:

amorphous insulating layers separating the sidewalls of the channel region from the secondary gate layer,

wherein the secondary gate layer is conductively coupled to the primary gate layers.

20. The field effect transistor of claim 8, further comprising:

source/drain regions on opposite ends of and conductively coupled to the channel region adjacent the gate stack thereon; and

amorphous insulating layers separating opposing sidewalls of the gate layer from the source/drain regions.

21-32. -32. (canceled)